Verilog_VGA/
Verilog_VGA/db/
Verilog_VGA/db/VGA.(0).cnf.cdb
Verilog_VGA/db/VGA.(0).cnf.hdb
Verilog_VGA/db/VGA.(1).cnf.cdb
Verilog_VGA/db/VGA.(1).cnf.hdb
Verilog_VGA/db/VGA.asm.qmsg
Verilog_VGA/db/VGA.asm_labs.ddb
Verilog_VGA/db/VGA.cbx.xml
Verilog_VGA/db/VGA.cmp.cdb
Verilog_VGA/db/VGA.cmp.hdb
Verilog_VGA/db/VGA.cmp.qrpt
Verilog_VGA/db/VGA.cmp.rdb
Verilog_VGA/db/VGA.cmp.tdb
Verilog_VGA/db/VGA.cmp0.ddb
Verilog_VGA/db/VGA.dbp
Verilog_VGA/db/VGA.db_info
Verilog_VGA/db/VGA.eco.cdb
Verilog_VGA/db/VGA.fit.qmsg
Verilog_VGA/db/VGA.hier_info
Verilog_VGA/db/VGA.hif
Verilog_VGA/db/VGA.map.cdb
Verilog_VGA/db/VGA.map.hdb
Verilog_VGA/db/VGA.map.qmsg
Verilog_VGA/db/VGA.pre_map.cdb
Verilog_VGA/db/VGA.pre_map.hdb
Verilog_VGA/db/VGA.psp
Verilog_VGA/db/VGA.rtlv.hdb
Verilog_VGA/db/VGA.rtlv_sg.cdb
Verilog_VGA/db/VGA.rtlv_sg_swap.cdb
Verilog_VGA/db/VGA.sgdiff.cdb
Verilog_VGA/db/VGA.sgdiff.hdb
Verilog_VGA/db/VGA.signalprobe.cdb
Verilog_VGA/db/VGA.sld_design_entry.sci
Verilog_VGA/db/VGA.sld_design_entry_dsc.sci
Verilog_VGA/db/VGA.syn_hier_info
Verilog_VGA/db/VGA.tan.qmsg
Verilog_VGA/setup.tcl
Verilog_VGA/VGA.asm.rpt
Verilog_VGA/VGA.bdf
Verilog_VGA/VGA.cdf
Verilog_VGA/VGA.done
Verilog_VGA/VGA.fit.eqn
Verilog_VGA/VGA.fit.rpt
Verilog_VGA/VGA.fit.summary
Verilog_VGA/VGA.flow.rpt
Verilog_VGA/VGA.map.eqn
Verilog_VGA/VGA.map.rpt
Verilog_VGA/VGA.map.summary
Verilog_VGA/VGA.pin
Verilog_VGA/VGA.pof
Verilog_VGA/VGA.qpf
Verilog_VGA/VGA.qsf
Verilog_VGA/VGA.qws
Verilog_VGA/VGA.sof
Verilog_VGA/VGA.tan.rpt
Verilog_VGA/VGA.tan.summary
Verilog_VGA/VGAsignal.bsf
Verilog_VGA/VGAsignal.v
Verilog_VGA/VGA_assignment_defaults.qdf