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文件名称:vhtoverilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-03-07
  • 文件大小：
    27.96mb
  • 已下载：
    0次
  • 提 供 者：
    shan*****
  • 相关连接：
    无
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

A major obstacle of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test

response compaction are the unknown values (x-values) captured

by scan cells during testing. If test responses with

x-values are compacted, some of the outputs of the compactor

may also take unknown values and the correctness of the

compactor inputs cannot be verified at the compactor outputs.

The presence of x-values hence reduces observability of (nonx)

scan cells that may lead to a reduction of test quality and/or

limited compaction rates-A major obstacle　of thge code is to convert verilog to convert an vhdl code that stands in the way of efficient test

response compaction are the unknown values (x-values) captured

by scan cells during testing. If test responses with

x-values are compacted, some of the outputs of the compactor

may also take unknown values and the correctness of the

compactor inputs cannot be verified at the compactor outputs.

The presence of x-values hence reduces observability of (nonx)

scan cells that may lead to a reduction of test quality and/or

limited compaction rates
(系统自动生成,下载前可以参看下载内容)

下载文件列表

vhtoverilog/14SEP2013/bin/verilog2vhdl
vhtoverilog/14SEP2013/bin/verilog2vhdl.bat
vhtoverilog/14SEP2013/bin/verilog2vhdlcomponent
vhtoverilog/14SEP2013/bin/verilog2vhdlcomponent.bat
vhtoverilog/14SEP2013/bin/verilog2vhdlentity
vhtoverilog/14SEP2013/bin/verilog2vhdlentity.bat
vhtoverilog/14SEP2013/examples/simple_and/output.v2vh.vhd
vhtoverilog/14SEP2013/examples/simple_and/runme.bat
vhtoverilog/14SEP2013/examples/simple_and/runme.csh
vhtoverilog/14SEP2013/examples/simple_and/simple_and.v
vhtoverilog/14SEP2013/examples/simple_and/simple_and.vhd
vhtoverilog/14SEP2013/examples/simple_and/verilog2vhdl.log
vhtoverilog/14SEP2013/lib/designplayer.jar
vhtoverilog/14SEP2013/LICENSE.txt
vhtoverilog/14SEP2013/log
vhtoverilog/14SEP2013/README.txt
vhtoverilog/14SEP2013/setup_env.bat
vhtoverilog/14SEP2013/setup_env.csh
vhtoverilog/14SEP2013/setup_env.sh
vhtoverilog/14SEP2013/sum
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/math_complex/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/math_complex/math_complex.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/math_real/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/math_real/math_real.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/numeric_bit/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/numeric_bit/numeric_bit.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/numeric_std/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/numeric_std/numeric_std.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_1164/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_1164/std_logic_1164.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_arith/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_arith/std_logic_arith.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_arith_ext/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_arith_ext/std_logic_arith_ext.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_misc/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_misc/std_logic_misc.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_signed/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_signed/std_logic_signed.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_textio/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_textio/std_logic_textio.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_unsigned/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/std_logic_unsigned/std_logic_unsigned.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/vital_primitives/vital_primitives.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/vital_timing/body.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/ieee/vital_timing/vital_timing.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_negedge_rst_negedge_clk/dff_async_negedge_rst_negedge_clk.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_negedge_rst_negedge_clk/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_negedge_rst_posedge_clk/dff_async_negedge_rst_posedge_clk.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_negedge_rst_posedge_clk/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_posedge_rst_negedge_clk/dff_async_posedge_rst_negedge_clk.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_posedge_rst_negedge_clk/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_posedge_rst_posedge_clk/dff_async_posedge_rst_posedge_clk.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_async_posedge_rst_posedge_clk/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_simple_negedge/dff_simple_negedge.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_simple_negedge/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_simple_posedge/dff_simple_posedge.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/dff_simple_posedge/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_and/fvp_prim_and.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_and/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_buf/fvp_prim_buf.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_buf/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_bufif0/fvp_prim_bufif0.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_bufif0/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_bufif1/fvp_prim_bufif1.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_bufif1/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_cmos/fvp_prim_cmos.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_cmos/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nand/fvp_prim_nand.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nand/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nmos/fvp_prim_nmos.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nmos/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nor/fvp_prim_nor.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_nor/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_not/fvp_prim_not.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_not/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_notif0/fvp_prim_notif0.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/lib/misc/fvp_prim_notif0/rtl.dmp
vhtoverilog/14SEP2013/vhdl_pkgs/li

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