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文件名称:1.1-led_div50m

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-05-16
  • 文件大小：
    411.59kb
  • 已下载：
    0次
  • 提 供 者：
    qia****
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FPGA控制LED示，采用VHDL和Verilog语言，两种语言控制-The FPGA control LED display, using VHDL and Verilog language, two language control
(系统自动生成,下载前可以参看下载内容)

下载文件列表

1.1 led_div50m/Verilog/db/div50m.(0).cnf.cdb
1.1 led_div50m/Verilog/db/div50m.(0).cnf.hdb
1.1 led_div50m/Verilog/db/div50m.asm.qmsg
1.1 led_div50m/Verilog/db/div50m.asm_labs.ddb
1.1 led_div50m/Verilog/db/div50m.cbx.xml
1.1 led_div50m/Verilog/db/div50m.cmp.bpm
1.1 led_div50m/Verilog/db/div50m.cmp.cdb
1.1 led_div50m/Verilog/db/div50m.cmp.ecobp
1.1 led_div50m/Verilog/db/div50m.cmp.hdb
1.1 led_div50m/Verilog/db/div50m.cmp.kpt
1.1 led_div50m/Verilog/db/div50m.cmp.logdb
1.1 led_div50m/Verilog/db/div50m.cmp.rdb
1.1 led_div50m/Verilog/db/div50m.cmp.tdb
1.1 led_div50m/Verilog/db/div50m.cmp0.ddb
1.1 led_div50m/Verilog/db/div50m.cmp2.ddb
1.1 led_div50m/Verilog/db/div50m.cmp_merge.kpt
1.1 led_div50m/Verilog/db/div50m.db_info
1.1 led_div50m/Verilog/db/div50m.eco.cdb
1.1 led_div50m/Verilog/db/div50m.fit.qmsg
1.1 led_div50m/Verilog/db/div50m.hier_info
1.1 led_div50m/Verilog/db/div50m.hif
1.1 led_div50m/Verilog/db/div50m.lpc.html
1.1 led_div50m/Verilog/db/div50m.lpc.rdb
1.1 led_div50m/Verilog/db/div50m.lpc.txt
1.1 led_div50m/Verilog/db/div50m.map.bpm
1.1 led_div50m/Verilog/db/div50m.map.cdb
1.1 led_div50m/Verilog/db/div50m.map.ecobp
1.1 led_div50m/Verilog/db/div50m.map.hdb
1.1 led_div50m/Verilog/db/div50m.map.kpt
1.1 led_div50m/Verilog/db/div50m.map.logdb
1.1 led_div50m/Verilog/db/div50m.map.qmsg
1.1 led_div50m/Verilog/db/div50m.map_bb.cdb
1.1 led_div50m/Verilog/db/div50m.map_bb.hdb
1.1 led_div50m/Verilog/db/div50m.map_bb.logdb
1.1 led_div50m/Verilog/db/div50m.pre_map.cdb
1.1 led_div50m/Verilog/db/div50m.pre_map.hdb
1.1 led_div50m/Verilog/db/div50m.rtlv.hdb
1.1 led_div50m/Verilog/db/div50m.rtlv_sg.cdb
1.1 led_div50m/Verilog/db/div50m.rtlv_sg_swap.cdb
1.1 led_div50m/Verilog/db/div50m.sgdiff.cdb
1.1 led_div50m/Verilog/db/div50m.sgdiff.hdb
1.1 led_div50m/Verilog/db/div50m.sim_ori.vwf
1.1 led_div50m/Verilog/db/div50m.sld_design_entry.sci
1.1 led_div50m/Verilog/db/div50m.sld_design_entry_dsc.sci
1.1 led_div50m/Verilog/db/div50m.syn_hier_info
1.1 led_div50m/Verilog/db/div50m.tan.qmsg
1.1 led_div50m/Verilog/db/div50m.tis_db_list.ddb
1.1 led_div50m/Verilog/db/div50m.tmw_info
1.1 led_div50m/Verilog/db/prev_cmp_div50m.asm.qmsg
1.1 led_div50m/Verilog/db/prev_cmp_div50m.fit.qmsg
1.1 led_div50m/Verilog/db/prev_cmp_div50m.map.qmsg
1.1 led_div50m/Verilog/db/prev_cmp_div50m.qmsg
1.1 led_div50m/Verilog/db/prev_cmp_div50m.sim.qmsg
1.1 led_div50m/Verilog/db/prev_cmp_div50m.tan.qmsg
1.1 led_div50m/Verilog/db/wed.wsf
1.1 led_div50m/Verilog/div50m.asm.rpt
1.1 led_div50m/Verilog/div50m.cdf
1.1 led_div50m/Verilog/div50m.done
1.1 led_div50m/Verilog/div50m.dpf
1.1 led_div50m/Verilog/div50m.fit.rpt
1.1 led_div50m/Verilog/div50m.fit.smsg
1.1 led_div50m/Verilog/div50m.fit.summary
1.1 led_div50m/Verilog/div50m.flow.rpt
1.1 led_div50m/Verilog/div50m.map.rpt
1.1 led_div50m/Verilog/div50m.map.summary
1.1 led_div50m/Verilog/div50m.pin
1.1 led_div50m/Verilog/div50m.pof
1.1 led_div50m/Verilog/div50m.qpf
1.1 led_div50m/Verilog/div50m.qsf
1.1 led_div50m/Verilog/div50m.qws
1.1 led_div50m/Verilog/div50m.sim.rpt
1.1 led_div50m/Verilog/div50m.sof
1.1 led_div50m/Verilog/div50m.tan.rpt
1.1 led_div50m/Verilog/div50m.tan.summary
1.1 led_div50m/Verilog/div50m.v
1.1 led_div50m/Verilog/div50m.v.bak
1.1 led_div50m/Verilog/div50m.vwf
1.1 led_div50m/Verilog/div50m_assignment_defaults.qdf
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.atm
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.dfp
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.hdbx
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.kpt
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.logdb
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.cmp.rcf
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.map.atm
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.map.dpi
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.map.hdbx
1.1 led_div50m/Verilog/incremental_db/compiled_partitions/div50m.root_partition.map.kpt
1.1 led_div50m/Verilog/incremental_db/README
1.1 led_div50m/Verilog/pin/CORE2-5SD.tcl
1.1 led_div50m/Verilog/pin/CORE2-5U.tcl
1.1 led_div50m/Verilog/pin/COREC-240U.tcl
1.1 led_div50m/VHDL/db/LED.db_info
1.1 led_div50m/VHDL/db/LED.eco.cdb
1.1 led_div50m/VHDL/db/LED.sld_design_entry.sci
1.1 led_div50m/VHDL/db/LED_global_asgn_op.abo
1.1 led_div50m/VHDL/db/prev_cmp_LED.asm.qmsg
1.1 led_div50m/VHDL/db/prev_cmp_LED.fit.qmsg
1.1 led_div50m/VHDL/db/prev_cmp_LED.map.qmsg
1.1 led_div50m/VHDL/db/prev_cmp_LED.qmsg
1.1 led_div50m/VHDL/db/prev_cmp_LED.tan.qmsg
1.1 led_div50m/VHDL/div50m.vhd
1.1 led_div50m/VHDL/div50m.vhd.bak
1.1 led_div50m/VHDL/incremental_db/compiled_partitions/LED.root_partition.cmp.atm
1.1 led_div50m/VHDL/incremental_db/compiled_partitions/LED.root_partition.cmp.dfp
1.1 led_div50m/VHDL/incremental_db/compiled_partitions/LED.root_partition.cmp.hdbx
1.1 led_div50m/VHDL/incremental_db/compiled_partitions/LED.root_partition.cmp.kpt
1.1 led

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