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文件名称:traffic-light-design

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-07-12
  • 文件大小：
    3.89mb
  • 已下载：
    0次
  • 提 供 者：
    逍*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于ISP的交通灯设计，实现了各路状态转换、警察控制、行人请求功能。-ISP traffic light design, to achieve the brightest state transitions, police control, pedestrian request feature.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

shiyan5(0976_2740)/automake.log
shiyan5(0976_2740)/clk_l.jhd
shiyan5(0976_2740)/clk_l.prj
shiyan5(0976_2740)/clk_l.srf
shiyan5(0976_2740)/clk_l.v
shiyan5(0976_2740)/dispay.jhd
shiyan5(0976_2740)/dispay.sch
shiyan5(0976_2740)/dither.bl0
shiyan5(0976_2740)/dither.bl1
shiyan5(0976_2740)/dither.cif
shiyan5(0976_2740)/dither.edi
shiyan5(0976_2740)/dither.exf
shiyan5(0976_2740)/dither.fse
shiyan5(0976_2740)/dither.jhd
shiyan5(0976_2740)/dither.log
shiyan5(0976_2740)/dither.naf
shiyan5(0976_2740)/dither.prj
shiyan5(0976_2740)/dither.srf
shiyan5(0976_2740)/dither.srm
shiyan5(0976_2740)/dither.srr
shiyan5(0976_2740)/dither.srs
shiyan5(0976_2740)/dither.sym
shiyan5(0976_2740)/dither.v
shiyan5(0976_2740)/dither1.bl0
shiyan5(0976_2740)/dither1.bl1
shiyan5(0976_2740)/dither1.cif
shiyan5(0976_2740)/dither1.edi
shiyan5(0976_2740)/dither1.exf
shiyan5(0976_2740)/dither1.fse
shiyan5(0976_2740)/dither1.jhd
shiyan5(0976_2740)/dither1.log
shiyan5(0976_2740)/dither1.naf
shiyan5(0976_2740)/dither1.prj
shiyan5(0976_2740)/dither1.srf
shiyan5(0976_2740)/dither1.srm
shiyan5(0976_2740)/dither1.srr
shiyan5(0976_2740)/dither1.srs
shiyan5(0976_2740)/dither1.sym
shiyan5(0976_2740)/dither1.v
shiyan5(0976_2740)/dm/dither1_compiler.xdm
shiyan5(0976_2740)/dm/dither_compiler.xdm
shiyan5(0976_2740)/dm/scan_compiler.xdm
shiyan5(0976_2740)/dm/state_compiler.xdm
shiyan5(0976_2740)/FANGZHEN.bin
shiyan5(0976_2740)/FANGZHEN.lt2
shiyan5(0976_2740)/fangzhen.ltv
shiyan5(0976_2740)/FANGZHEN.nam
shiyan5(0976_2740)/fangzhen.slg
shiyan5(0976_2740)/fangzhen.trf
shiyan5(0976_2740)/FANGZHEN.wav
shiyan5(0976_2740)/fangzhen.wdl
shiyan5(0976_2740)/fangzhen.wet
shiyan5(0976_2740)/lattice_cmd.rs2
shiyan5(0976_2740)/LCIEdit.dum
shiyan5(0976_2740)/lciedit.log
shiyan5(0976_2740)/ltsim.log
shiyan5(0976_2740)/rev_1/backup/shiyan5_0976_2740.srr
shiyan5(0976_2740)/rev_1/dm/shiyan5_0976_2740_compiler.xdm
shiyan5(0976_2740)/rev_1/run_options.txt
shiyan5(0976_2740)/rev_1/scratchproject.prs
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.edf
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.fse
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.htm
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.srm
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.srr
shiyan5(0976_2740)/rev_1/shiyan5_0976_2740.srs
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_errors.msg
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_errors.txt
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_notes.txt
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_runstatus.xml
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_warnings.msg
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_compiler_warnings.txt
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_fpga_mapper_errors.txt
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_fpga_mapper_notes.txt
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_fpga_mapper_runstatus.xml
shiyan5(0976_2740)/rev_1/synlog/report/shiyan5_0976_2740_fpga_mapper_warnings.txt
shiyan5(0976_2740)/rev_1/synlog/shiyan5_0976_2740_fpga_mapper.srr
shiyan5(0976_2740)/rev_1/syntmp/closed.png
shiyan5(0976_2740)/rev_1/syntmp/cmdrec_compiler.log
shiyan5(0976_2740)/rev_1/syntmp/cmdrec_fpga_mapper.log
shiyan5(0976_2740)/rev_1/syntmp/open.png
shiyan5(0976_2740)/rev_1/syntmp/run_option.xml
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740.msg
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740.plg
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_compiler_errors_txt_report.htm
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_compiler_warnings_txt_report.htm
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_flink.htm
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_fpga_mapper.msg
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_srr.htm
shiyan5(0976_2740)/rev_1/syntmp/shiyan5_0976_2740_toc.htm
shiyan5(0976_2740)/rev_1/synwork/shiyan5_0976_2740_compiler.fdep
shiyan5(0976_2740)/rev_1/synwork/shiyan5_0976_2740_compiler.srs
shiyan5(0976_2740)/rev_1/synwork/shiyan5_0976_2740_compiler.tlg
shiyan5(0976_2740)/rev_2/backup/shiyan5_0976_2740.srr
shiyan5(0976_2740)/rev_2/dm/shiyan5_0976_2740_compiler.xdm
shiyan5(0976_2740)/rev_2/run_options.txt
shiyan5(0976_2740)/rev_2/scratchproject.prs
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.edf
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.fse
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.htm
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.srm
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.srr
shiyan5(0976_2740)/rev_2/shiyan5_0976_2740.srs
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_errors.msg
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_errors.txt
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_notes.txt
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_runstatus.xml
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_warnings.msg
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_compiler_warnings.txt
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976_2740_fpga_mapper_errors.txt
shiyan5(0976_2740)/rev_2/synlog/report/shiyan5_0976

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