文件名称:LCD1602
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- 上传时间:2015-06-26
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文件大小:360.41kb
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Verilog 语言 CPLD 控制液晶自定义输出程序,可仿真,可转换电路原理图。-Verilog language CPLD control LCD custom output procedures, can be simulated, can be converted to circuit schematics.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LCD1602/db/.cmp.kpt
LCD1602/db/lcd1602.(0).cnf.cdb
LCD1602/db/lcd1602.(0).cnf.hdb
LCD1602/db/lcd1602.(1).cnf.cdb
LCD1602/db/lcd1602.(1).cnf.hdb
LCD1602/db/lcd1602.asm.qmsg
LCD1602/db/lcd1602.asm.rdb
LCD1602/db/lcd1602.asm_labs.ddb
LCD1602/db/lcd1602.cbx.xml
LCD1602/db/lcd1602.cmp.cdb
LCD1602/db/lcd1602.cmp.hdb
LCD1602/db/lcd1602.cmp.idb
LCD1602/db/lcd1602.cmp.logdb
LCD1602/db/lcd1602.cmp.rdb
LCD1602/db/lcd1602.cmp0.ddb
LCD1602/db/lcd1602.db_info
LCD1602/db/lcd1602.eda.qmsg
LCD1602/db/lcd1602.fit.qmsg
LCD1602/db/lcd1602.hier_info
LCD1602/db/lcd1602.hif
LCD1602/db/lcd1602.logic_util_heuristic.dat
LCD1602/db/lcd1602.lpc.html
LCD1602/db/lcd1602.lpc.rdb
LCD1602/db/lcd1602.lpc.txt
LCD1602/db/lcd1602.map.cdb
LCD1602/db/lcd1602.map.hdb
LCD1602/db/lcd1602.map.logdb
LCD1602/db/lcd1602.map.qmsg
LCD1602/db/lcd1602.map.rdb
LCD1602/db/lcd1602.pplq.rdb
LCD1602/db/lcd1602.pre_map.hdb
LCD1602/db/lcd1602.pti_db_list.ddb
LCD1602/db/lcd1602.ram0_LCD1602_4c82a4e3.hdl.mif
LCD1602/db/lcd1602.ram1_LCD1602_4c82a4e3.hdl.mif
LCD1602/db/lcd1602.root_partition.map.reg_db.cdb
LCD1602/db/lcd1602.routing.rdb
LCD1602/db/lcd1602.rtlv.hdb
LCD1602/db/lcd1602.rtlv_sg.cdb
LCD1602/db/lcd1602.rtlv_sg_swap.cdb
LCD1602/db/lcd1602.sld_design_entry.sci
LCD1602/db/lcd1602.sld_design_entry_dsc.sci
LCD1602/db/lcd1602.smart_action.txt
LCD1602/db/lcd1602.smp_dump.txt
LCD1602/db/lcd1602.sta.qmsg
LCD1602/db/lcd1602.sta.rdb
LCD1602/db/lcd1602.sta_cmp.5_slow.tdb
LCD1602/db/lcd1602.tis_db_list.ddb
LCD1602/db/lcd1602.tmw_info
LCD1602/db/lcd1602.vpr.ammdb
LCD1602/db/logic_util_heursitic.dat
LCD1602/db/prev_cmp_lcd1602.asm.qmsg
LCD1602/db/prev_cmp_lcd1602.fit.qmsg
LCD1602/db/prev_cmp_lcd1602.map.qmsg
LCD1602/db/prev_cmp_lcd1602.qmsg
LCD1602/db/prev_cmp_lcd1602.tan.qmsg
LCD1602/incremental_db/compiled_partitions/lcd1602.db_info
LCD1602/incremental_db/compiled_partitions/lcd1602.root_partition.map.kpt
LCD1602/incremental_db/README
LCD1602/lcd1602.asm.rpt
LCD1602/LCD1602.bsf
LCD1602/lcd1602.cdf
LCD1602/lcd1602.done
LCD1602/lcd1602.eda.rpt
LCD1602/lcd1602.fit.rpt
LCD1602/lcd1602.fit.smsg
LCD1602/lcd1602.fit.summary
LCD1602/lcd1602.flow.rpt
LCD1602/lcd1602.jdi
LCD1602/lcd1602.map.rpt
LCD1602/lcd1602.map.smsg
LCD1602/lcd1602.map.summary
LCD1602/lcd1602.pin
LCD1602/lcd1602.pof
LCD1602/lcd1602.qpf
LCD1602/lcd1602.qsf
LCD1602/lcd1602.qsf.bak
LCD1602/lcd1602.qws
LCD1602/lcd1602.sld
LCD1602/lcd1602.sta.rpt
LCD1602/lcd1602.sta.summary
LCD1602/lcd1602.tan.rpt
LCD1602/lcd1602.tan.summary
LCD1602/LCD1602.v
LCD1602/LCD1602.v.bak
LCD1602/lcd1602_assignment_defaults.qdf
LCD1602/lcd1602_nativelink_simulation.rpt
LCD1602/LCD1602_TEST.v.bak
LCD1602/out.bsf
LCD1602/out.v
LCD1602/out.v.bak
LCD1602/simulation/modelsim/lcd1602.sft
LCD1602/simulation/modelsim/lcd1602.vo
LCD1602/simulation/modelsim/lcd1602_modelsim.xrf
LCD1602/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do
LCD1602/simulation/modelsim/lcd1602_v.sdo
LCD1602/simulation/modelsim/modelsim.ini
LCD1602/simulation/modelsim/msim_transcript
LCD1602/simulation/modelsim/rtl_work/_info
LCD1602/simulation/modelsim/rtl_work/_lib.qdb
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qdb
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qpg
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qtl
LCD1602/simulation/modelsim/rtl_work/_vmake
LCD1602/XIANSHI.bdf
LCD1602/simulation/modelsim/rtl_work
LCD1602/incremental_db/compiled_partitions
LCD1602/simulation/modelsim
LCD1602/db
LCD1602/incremental_db
LCD1602/simulation
LCD1602
LCD1602/db/lcd1602.(0).cnf.cdb
LCD1602/db/lcd1602.(0).cnf.hdb
LCD1602/db/lcd1602.(1).cnf.cdb
LCD1602/db/lcd1602.(1).cnf.hdb
LCD1602/db/lcd1602.asm.qmsg
LCD1602/db/lcd1602.asm.rdb
LCD1602/db/lcd1602.asm_labs.ddb
LCD1602/db/lcd1602.cbx.xml
LCD1602/db/lcd1602.cmp.cdb
LCD1602/db/lcd1602.cmp.hdb
LCD1602/db/lcd1602.cmp.idb
LCD1602/db/lcd1602.cmp.logdb
LCD1602/db/lcd1602.cmp.rdb
LCD1602/db/lcd1602.cmp0.ddb
LCD1602/db/lcd1602.db_info
LCD1602/db/lcd1602.eda.qmsg
LCD1602/db/lcd1602.fit.qmsg
LCD1602/db/lcd1602.hier_info
LCD1602/db/lcd1602.hif
LCD1602/db/lcd1602.logic_util_heuristic.dat
LCD1602/db/lcd1602.lpc.html
LCD1602/db/lcd1602.lpc.rdb
LCD1602/db/lcd1602.lpc.txt
LCD1602/db/lcd1602.map.cdb
LCD1602/db/lcd1602.map.hdb
LCD1602/db/lcd1602.map.logdb
LCD1602/db/lcd1602.map.qmsg
LCD1602/db/lcd1602.map.rdb
LCD1602/db/lcd1602.pplq.rdb
LCD1602/db/lcd1602.pre_map.hdb
LCD1602/db/lcd1602.pti_db_list.ddb
LCD1602/db/lcd1602.ram0_LCD1602_4c82a4e3.hdl.mif
LCD1602/db/lcd1602.ram1_LCD1602_4c82a4e3.hdl.mif
LCD1602/db/lcd1602.root_partition.map.reg_db.cdb
LCD1602/db/lcd1602.routing.rdb
LCD1602/db/lcd1602.rtlv.hdb
LCD1602/db/lcd1602.rtlv_sg.cdb
LCD1602/db/lcd1602.rtlv_sg_swap.cdb
LCD1602/db/lcd1602.sld_design_entry.sci
LCD1602/db/lcd1602.sld_design_entry_dsc.sci
LCD1602/db/lcd1602.smart_action.txt
LCD1602/db/lcd1602.smp_dump.txt
LCD1602/db/lcd1602.sta.qmsg
LCD1602/db/lcd1602.sta.rdb
LCD1602/db/lcd1602.sta_cmp.5_slow.tdb
LCD1602/db/lcd1602.tis_db_list.ddb
LCD1602/db/lcd1602.tmw_info
LCD1602/db/lcd1602.vpr.ammdb
LCD1602/db/logic_util_heursitic.dat
LCD1602/db/prev_cmp_lcd1602.asm.qmsg
LCD1602/db/prev_cmp_lcd1602.fit.qmsg
LCD1602/db/prev_cmp_lcd1602.map.qmsg
LCD1602/db/prev_cmp_lcd1602.qmsg
LCD1602/db/prev_cmp_lcd1602.tan.qmsg
LCD1602/incremental_db/compiled_partitions/lcd1602.db_info
LCD1602/incremental_db/compiled_partitions/lcd1602.root_partition.map.kpt
LCD1602/incremental_db/README
LCD1602/lcd1602.asm.rpt
LCD1602/LCD1602.bsf
LCD1602/lcd1602.cdf
LCD1602/lcd1602.done
LCD1602/lcd1602.eda.rpt
LCD1602/lcd1602.fit.rpt
LCD1602/lcd1602.fit.smsg
LCD1602/lcd1602.fit.summary
LCD1602/lcd1602.flow.rpt
LCD1602/lcd1602.jdi
LCD1602/lcd1602.map.rpt
LCD1602/lcd1602.map.smsg
LCD1602/lcd1602.map.summary
LCD1602/lcd1602.pin
LCD1602/lcd1602.pof
LCD1602/lcd1602.qpf
LCD1602/lcd1602.qsf
LCD1602/lcd1602.qsf.bak
LCD1602/lcd1602.qws
LCD1602/lcd1602.sld
LCD1602/lcd1602.sta.rpt
LCD1602/lcd1602.sta.summary
LCD1602/lcd1602.tan.rpt
LCD1602/lcd1602.tan.summary
LCD1602/LCD1602.v
LCD1602/LCD1602.v.bak
LCD1602/lcd1602_assignment_defaults.qdf
LCD1602/lcd1602_nativelink_simulation.rpt
LCD1602/LCD1602_TEST.v.bak
LCD1602/out.bsf
LCD1602/out.v
LCD1602/out.v.bak
LCD1602/simulation/modelsim/lcd1602.sft
LCD1602/simulation/modelsim/lcd1602.vo
LCD1602/simulation/modelsim/lcd1602_modelsim.xrf
LCD1602/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do
LCD1602/simulation/modelsim/lcd1602_v.sdo
LCD1602/simulation/modelsim/modelsim.ini
LCD1602/simulation/modelsim/msim_transcript
LCD1602/simulation/modelsim/rtl_work/_info
LCD1602/simulation/modelsim/rtl_work/_lib.qdb
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qdb
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qpg
LCD1602/simulation/modelsim/rtl_work/_lib1_0.qtl
LCD1602/simulation/modelsim/rtl_work/_vmake
LCD1602/XIANSHI.bdf
LCD1602/simulation/modelsim/rtl_work
LCD1602/incremental_db/compiled_partitions
LCD1602/simulation/modelsim
LCD1602/db
LCD1602/incremental_db
LCD1602/simulation
LCD1602
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