CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:EP1C3-uart_1_verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-03-09
  • 文件大小：
    333.85kb
  • 已下载：
    0次
  • 提 供 者：
    davi****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。

串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值

是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通

信同步.-EP1C3-uart 1 verilog, implements a program to send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit.

Baud-law decided by div_par parameters defined in the program, you can change the parameters to achieve the appropriate baud rate. Value of the program is currently set div_par

Is 0x145, the corresponding baud rate is 9600. An 8 times the baud rate clock to send or receive every bit of the time period is divided into eight time slots so that the pass

Letter synchronization.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

demo7-uart_1_verilog/db/prev_cmp_serial_1.asm.qmsg
demo7-uart_1_verilog/db/prev_cmp_serial_1.fit.qmsg
demo7-uart_1_verilog/db/prev_cmp_serial_1.map.qmsg
demo7-uart_1_verilog/db/prev_cmp_serial_1.qmsg
demo7-uart_1_verilog/db/prev_cmp_serial_1.tan.qmsg
demo7-uart_1_verilog/db/serial_1.(0).cnf.cdb
demo7-uart_1_verilog/db/serial_1.(0).cnf.hdb
demo7-uart_1_verilog/db/serial_1.asm.qmsg
demo7-uart_1_verilog/db/serial_1.cbx.xml
demo7-uart_1_verilog/db/serial_1.cmp.ecobp
demo7-uart_1_verilog/db/serial_1.cmp.kpt
demo7-uart_1_verilog/db/serial_1.cmp.rdb
demo7-uart_1_verilog/db/serial_1.cmp0.ddb
demo7-uart_1_verilog/db/serial_1.cmp_merge.kpt
demo7-uart_1_verilog/db/serial_1.db_info
demo7-uart_1_verilog/db/serial_1.eco.cdb
demo7-uart_1_verilog/db/serial_1.fit.qmsg
demo7-uart_1_verilog/db/serial_1.hier_info
demo7-uart_1_verilog/db/serial_1.hif
demo7-uart_1_verilog/db/serial_1.lpc.html
demo7-uart_1_verilog/db/serial_1.lpc.rdb
demo7-uart_1_verilog/db/serial_1.lpc.txt
demo7-uart_1_verilog/db/serial_1.map.bpm
demo7-uart_1_verilog/db/serial_1.map.cdb
demo7-uart_1_verilog/db/serial_1.map.ecobp
demo7-uart_1_verilog/db/serial_1.map.hdb
demo7-uart_1_verilog/db/serial_1.map.kpt
demo7-uart_1_verilog/db/serial_1.map.logdb
demo7-uart_1_verilog/db/serial_1.map.qmsg
demo7-uart_1_verilog/db/serial_1.map_bb.cdb
demo7-uart_1_verilog/db/serial_1.map_bb.hdb
demo7-uart_1_verilog/db/serial_1.map_bb.logdb
demo7-uart_1_verilog/db/serial_1.pre_map.cdb
demo7-uart_1_verilog/db/serial_1.pre_map.hdb
demo7-uart_1_verilog/db/serial_1.rtlv.hdb
demo7-uart_1_verilog/db/serial_1.rtlv_sg.cdb
demo7-uart_1_verilog/db/serial_1.rtlv_sg_swap.cdb
demo7-uart_1_verilog/db/serial_1.sgdiff.cdb
demo7-uart_1_verilog/db/serial_1.sgdiff.hdb
demo7-uart_1_verilog/db/serial_1.sld_design_entry.sci
demo7-uart_1_verilog/db/serial_1.sld_design_entry_dsc.sci
demo7-uart_1_verilog/db/serial_1.syn_hier_info
demo7-uart_1_verilog/db/serial_1.tan.qmsg
demo7-uart_1_verilog/db/serial_1.tis_db_list.ddb
demo7-uart_1_verilog/db/serial_1.tmw_info
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.atm
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.dfp
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.hdbx
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.kpt
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.logdb
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.cmp.rcf
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.map.atm
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.map.dpi
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.map.hdbx
demo7-uart_1_verilog/incremental_db/compiled_partitions/serial_1.root_partition.map.kpt
demo7-uart_1_verilog/incremental_db/README
demo7-uart_1_verilog/serial_1.asm.rpt
demo7-uart_1_verilog/serial_1.done
demo7-uart_1_verilog/serial_1.dpf
demo7-uart_1_verilog/serial_1.fit.rpt
demo7-uart_1_verilog/serial_1.fit.smsg
demo7-uart_1_verilog/serial_1.fit.summary
demo7-uart_1_verilog/serial_1.flow.rpt
demo7-uart_1_verilog/serial_1.map.rpt
demo7-uart_1_verilog/serial_1.map.summary
demo7-uart_1_verilog/serial_1.pin
demo7-uart_1_verilog/serial_1.pof
demo7-uart_1_verilog/serial_1.qpf
demo7-uart_1_verilog/serial_1.qsf
demo7-uart_1_verilog/serial_1.qws
demo7-uart_1_verilog/serial_1.sof
demo7-uart_1_verilog/serial_1.tan.rpt
demo7-uart_1_verilog/serial_1.tan.summary
demo7-uart_1_verilog/serial_1.v
demo7-uart_1_verilog/incremental_db/compiled_partitions
demo7-uart_1_verilog/db
demo7-uart_1_verilog/incremental_db
demo7-uart_1_verilog

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com