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文件名称:design-IR-Verilog

  • 所属分类：
    VHDL/FPGA/Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2017-07-15
  • 文件大小：
    9.6mb
  • 已下载：
    0次
  • 提 供 者：
    神通***
  • 相关连接：
    无
  • 下载说明：
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修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

IR传感器使用Verilog语言编程，平台实在FPGA Cycle 4上实现(IR sensor using Verilog programming language, the platform is really FPGA Cycle 4 implementation)
相关搜索： IR传感器使用 Verilog语言 fpga

(系统自动生成,下载前可以参看下载内容)

下载文件列表

design-IR-Verilog/beep.v
design-IR-Verilog/db/altsyncram_2r14.tdf
design-IR-Verilog/db/altsyncram_4r14.tdf
design-IR-Verilog/db/beep.map_bb.logdb
design-IR-Verilog/db/beep.smp_dump.txt
design-IR-Verilog/db/cmpr_ngc.tdf
design-IR-Verilog/db/cmpr_qgc.tdf
design-IR-Verilog/db/cntr_23j.tdf
design-IR-Verilog/db/cntr_egi.tdf
design-IR-Verilog/db/cntr_i6j.tdf
design-IR-Verilog/db/decode_dvf.tdf
design-IR-Verilog/db/dt.map_bb.logdb
design-IR-Verilog/db/dt.smp_dump.txt
design-IR-Verilog/db/IR.map_bb.logdb
design-IR-Verilog/db/IR.smp_dump.txt
design-IR-Verilog/db/key.map_bb.logdb
design-IR-Verilog/db/key.smp_dump.txt
design-IR-Verilog/db/led.map_bb.logdb
design-IR-Verilog/db/led.smp_dump.txt
design-IR-Verilog/db/logic_util_heursitic.dat
design-IR-Verilog/db/mux_ssc.tdf
design-IR-Verilog/db/prev_cmp_beep.qmsg
design-IR-Verilog/db/prev_cmp_dt.qmsg
design-IR-Verilog/db/prev_cmp_IR.qmsg
design-IR-Verilog/db/prev_cmp_key.qmsg
design-IR-Verilog/db/prev_cmp_led.qmsg
design-IR-Verilog/db/top.(0).cnf.cdb
design-IR-Verilog/db/top.(0).cnf.hdb
design-IR-Verilog/db/top.(1).cnf.cdb
design-IR-Verilog/db/top.(1).cnf.hdb
design-IR-Verilog/db/top.(10).cnf.cdb
design-IR-Verilog/db/top.(10).cnf.hdb
design-IR-Verilog/db/top.(11).cnf.cdb
design-IR-Verilog/db/top.(11).cnf.hdb
design-IR-Verilog/db/top.(12).cnf.cdb
design-IR-Verilog/db/top.(12).cnf.hdb
design-IR-Verilog/db/top.(13).cnf.cdb
design-IR-Verilog/db/top.(13).cnf.hdb
design-IR-Verilog/db/top.(14).cnf.cdb
design-IR-Verilog/db/top.(14).cnf.hdb
design-IR-Verilog/db/top.(15).cnf.cdb
design-IR-Verilog/db/top.(15).cnf.hdb
design-IR-Verilog/db/top.(16).cnf.cdb
design-IR-Verilog/db/top.(16).cnf.hdb
design-IR-Verilog/db/top.(17).cnf.cdb
design-IR-Verilog/db/top.(17).cnf.hdb
design-IR-Verilog/db/top.(18).cnf.cdb
design-IR-Verilog/db/top.(18).cnf.hdb
design-IR-Verilog/db/top.(19).cnf.cdb
design-IR-Verilog/db/top.(19).cnf.hdb
design-IR-Verilog/db/top.(2).cnf.cdb
design-IR-Verilog/db/top.(2).cnf.hdb
design-IR-Verilog/db/top.(20).cnf.cdb
design-IR-Verilog/db/top.(20).cnf.hdb
design-IR-Verilog/db/top.(21).cnf.cdb
design-IR-Verilog/db/top.(21).cnf.hdb
design-IR-Verilog/db/top.(22).cnf.cdb
design-IR-Verilog/db/top.(22).cnf.hdb
design-IR-Verilog/db/top.(23).cnf.cdb
design-IR-Verilog/db/top.(23).cnf.hdb
design-IR-Verilog/db/top.(24).cnf.cdb
design-IR-Verilog/db/top.(24).cnf.hdb
design-IR-Verilog/db/top.(25).cnf.cdb
design-IR-Verilog/db/top.(25).cnf.hdb
design-IR-Verilog/db/top.(26).cnf.cdb
design-IR-Verilog/db/top.(26).cnf.hdb
design-IR-Verilog/db/top.(27).cnf.cdb
design-IR-Verilog/db/top.(27).cnf.hdb
design-IR-Verilog/db/top.(28).cnf.cdb
design-IR-Verilog/db/top.(28).cnf.hdb
design-IR-Verilog/db/top.(29).cnf.cdb
design-IR-Verilog/db/top.(29).cnf.hdb
design-IR-Verilog/db/top.(3).cnf.cdb
design-IR-Verilog/db/top.(3).cnf.hdb
design-IR-Verilog/db/top.(30).cnf.cdb
design-IR-Verilog/db/top.(30).cnf.hdb
design-IR-Verilog/db/top.(31).cnf.cdb
design-IR-Verilog/db/top.(31).cnf.hdb
design-IR-Verilog/db/top.(32).cnf.cdb
design-IR-Verilog/db/top.(32).cnf.hdb
design-IR-Verilog/db/top.(33).cnf.cdb
design-IR-Verilog/db/top.(33).cnf.hdb
design-IR-Verilog/db/top.(34).cnf.cdb
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design-IR-Verilog/db/top.(35).cnf.cdb
design-IR-Verilog/db/top.(35).cnf.hdb
design-IR-Verilog/db/top.(36).cnf.cdb
design-IR-Verilog/db/top.(36).cnf.hdb
design-IR-Verilog/db/top.(37).cnf.cdb
design-IR-Verilog/db/top.(37).cnf.hdb
design-IR-Verilog/db/top.(38).cnf.cdb
design-IR-Verilog/db/top.(38).cnf.hdb
design-IR-Verilog/db/top.(39).cnf.cdb
design-IR-Verilog/db/top.(39).cnf.hdb
design-IR-Verilog/db/top.(4).cnf.cdb
design-IR-Verilog/db/top.(4).cnf.hdb
design-IR-Verilog/db/top.(40).cnf.cdb
design-IR-Verilog/db/top.(40).cnf.hdb
design-IR-Verilog/db/top.(41).cnf.cdb
design-IR-Verilog/db/top.(41).cnf.hdb
design-IR-Verilog/db/top.(42).cnf.cdb
design-IR-Verilog/db/top.(42).cnf.hdb
design-IR-Verilog/db/top.(43).cnf.cdb
design-IR-Verilog/db/top.(43).cnf.hdb
design-IR-Verilog/db/top.(44).cnf.cdb
design-IR-Verilog/db/top.(44).cnf.hdb
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design-IR-Verilog/db/top.(46).cnf.cdb
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design-IR-Verilog/db/top.(47).cnf.cdb
design-IR-Verilog/db/top.(47).cnf.hdb
design-IR-Verilog/db/top.(48).cnf.cdb
design-IR-Verilog/db/top.(48).cnf.hdb
design-IR-Verilog/db/top.(49).cnf.cdb
design-IR-Verilog/db/top.(49).cnf.hdb
design-IR-Verilog/db/top.(5).cnf.cdb
design-IR-Verilog/db/top.(5).cnf.hdb
design-IR-Verilog/db/top.(50).cnf.cdb
design-IR-Verilog/db/top.(50).cnf.hdb
design-IR-Verilog/db/top.(51).cnf.cdb
design-IR-Verilog/db/top.(51).cnf.hdb
design-IR-Verilog/db/top.(52).cnf.cdb
design-IR-Verilog/db/top.(52).cnf.hdb
design-IR-Verilog/db/top.(53).cnf.cdb
design-IR-Verilog/db/top.(53).cnf.hdb
design-IR-Verilog/db/top.(54).cnf.cdb
design-IR-Verilog/db/top.(54).cnf.hdb
design-IR-Verilog/db/top.(55).cnf.cdb
design-IR-Verilog/db/top.(55).cnf.hdb
design-IR-Verilog/db/top.(56).cnf.cdb
design-IR-Verilog/db/top.(56).cnf.hdb
design-IR-Verilog/db/top.(57).cnf.cdb
design-IR-Verilog/db/top.(57).cnf.hdb
design-IR-Verilog/db/top.(6).cnf.cdb
design-IR-Verilog/db/top.(6

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