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文件名称:fpga_can_read_write

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    2018-12-10
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    81kb
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FPGA实现can通讯 已经调试成功 mcp1050(FPGA realizes can communication)
相关搜索: fpga CAN verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

文件名大小更新时间
fpga_can_read_write\db\fpga_can_read_write.db_info 140 2017-12-05
fpga_can_read_write\db\fpga_can_read_write.sld_design_entry.sci 223 2017-12-05
fpga_can_read_write\db\logic_util_heursitic.dat 0 2017-09-20
fpga_can_read_write\db\prev_cmp_fpga_can_read_write.qmsg 8613 2017-09-20
fpga_can_read_write\fpga_can_read_write.qpf 1309 2017-09-13
fpga_can_read_write\fpga_can_read_write.qsf 3240 2017-12-05
fpga_can_read_write\fpga_can_read_write.qws 670 2017-12-05
fpga_can_read_write\fpga_can_read_write.v 2460 2017-09-25
fpga_can_read_write\fpga_can_read_write.v.bak 527 2017-09-13
fpga_can_read_write\fpga_can_read_write_assignment_defaults.qdf 54528 2017-12-05
fpga_can_read_write\incremental_db\compiled_partitions\fpga_can_read_write.db_info 140 2017-12-05
fpga_can_read_write\incremental_db\compiled_partitions\fpga_can_read_write.root_partition.map.dpi 693 2017-09-20
fpga_can_read_write\incremental_db\compiled_partitions\fpga_can_read_write.root_partition.map.kpt 744 2017-09-20
fpga_can_read_write\incremental_db\README 653 2017-09-13
fpga_can_read_write\output_files\fpga_can_read_write.done 26 2017-09-20
fpga_can_read_write\output_files\fpga_can_read_write.eda.rpt 5958 2017-09-20
fpga_can_read_write\output_files\fpga_can_read_write.flow.rpt 8930 2017-09-20
fpga_can_read_write\output_files\fpga_can_read_write.map.rpt 24743 2017-09-20
fpga_can_read_write\output_files\fpga_can_read_write.map.smsg 141 2017-09-20
fpga_can_read_write\output_files\fpga_can_read_write.map.summary 495 2017-09-20
fpga_can_read_write\simulation\modelsim\fpga_can_read_write.sft 43 2017-09-20
fpga_can_read_write\simulation\modelsim\fpga_can_read_write.vo 15348 2017-09-20
fpga_can_read_write\simulation\modelsim\fpga_can_read_write_modelsim.xrf 2397 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.do 427 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.msim.vcd 9194 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.msim.vwf 58759 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.sim.vwf 13256 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.vo 15348 2017-09-20
fpga_can_read_write\simulation\qsim\fpga_can_read_write.vt 12720 2017-09-20
fpga_can_read_write\simulation\qsim\transcript 1254 2017-09-20
fpga_can_read_write\simulation\qsim\vsim.wlf 73728 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write\verilog.prw 2697 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write\verilog.psm 62048 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write\_primary.dat 10655 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write\_primary.dbs 11226 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write\_primary.vhd 434 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst\verilog.prw 2810 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst\verilog.psm 60536 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst\_primary.dat 6515 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst\_primary.dbs 4659 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst\_primary.vhd 462 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst\verilog.prw 324 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst\verilog.psm 5192 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst\_primary.dat 449 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst\_primary.dbs 608 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst\_primary.vhd 230 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst\verilog.prw 390 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst\verilog.psm 6432 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst\_primary.dat 833 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst\_primary.dbs 1132 2017-09-20
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst\_primary.vhd 122 2017-09-20
fpga_can_read_write\simulation\qsim\work\_info 1243 2017-09-20
fpga_can_read_write\simulation\qsim\work\_temp\vlognfxma6 941 2017-09-14
fpga_can_read_write\simulation\qsim\work\_vmake 26 2017-09-20
fpga_can_read_write\Waveform.vwf 6787 2017-09-14
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write 0 2017-11-12
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_check_tst 0 2017-11-12
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_sample_tst 0 2017-11-12
fpga_can_read_write\simulation\qsim\work\fpga_can_read_write_vlg_vec_tst 0 2017-11-12
fpga_can_read_write\simulation\qsim\work\_temp 0 2017-11-12
fpga_can_read_write\simulation\qsim\work 0 2017-11-12
fpga_can_read_write\incremental_db\compiled_partitions 0 2017-12-05
fpga_can_read_write\simulation\modelsim 0 2017-11-12
fpga_can_read_write\simulation\qsim 0 2017-11-12
fpga_can_read_write\db 0 2017-12-05
fpga_can_read_write\incremental_db 0 2017-11-12
fpga_can_read_write\output_files 0 2017-11-12
fpga_can_read_write\simulation 0 2017-11-12
fpga_can_read_write 0 2017-12-05

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