文件名称:dpd_v6_0_example_design
介绍说明--下载内容来自于网络,使用问题请自行百度
rtl代码级的dpd 参考代码
包含六个文件夹分别为:
1.clk_gen
2.device,器件信息
3.dpd v6.0,rtl代码.
4.package
5.platform
6.rf_board
包含六个文件夹分别为:
1.clk_gen
2.device,器件信息
3.dpd v6.0,rtl代码.
4.package
5.platform
6.rf_board
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : dpd_v6_0_example_design.zip 列表 dpd_v6_0_example_design/dfe_base.prj dpd_v6_0_example_design/dfe_base.vhd dpd_v6_0_example_design/dpd_v6_0_demo_msdpdgen1p5.cgp dpd_v6_0_example_design/dpd_v6_0_demo_msdpdgen1p5.ucf dpd_v6_0_example_design/dpd_v6_0_demo_msdpdgen1p5.xst dpd_v6_0_example_design/dpd_v6_0_inst.xco dpd_v6_0_example_design/iter6_pc_cfr_v3_0.xco dpd_v6_0_example_design/Makefile dpd_v6_0_example_design/src/ dpd_v6_0_example_design/src/clk_gen/ dpd_v6_0_example_design/src/clk_gen/hdl/ dpd_v6_0_example_design/src/clk_gen/hdl/clk_gen_src368mhz.vhd dpd_v6_0_example_design/src/clk_gen/hdl/data_path_clk_gen_src200mhz.vhd dpd_v6_0_example_design/src/clk_gen/hdl/proc_clk_gen_src200mhz.vhd dpd_v6_0_example_design/src/device/ dpd_v6_0_example_design/src/device/common/ dpd_v6_0_example_design/src/device/common/hdl/ dpd_v6_0_example_design/src/device/common/hdl/dfe_capture_control.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_complex_fir.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_complex_fir_x0_h0h1.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_complex_fir_x0x1_h0.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_config_registers.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_dlb.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_dlb_wrapper.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_dpram_piped_rtl.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_fh_gen_adder_12x16bit.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_fh_gen_adder_3x48bit.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_gain_iq_mult.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_generic_equalizer.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_glitch_protection.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_pipeliner.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_polyphase_complex_fir.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_rate_change.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_systolic_fir.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_systolic_fir_preadd_coeffs.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_systolic_fir_preadd_data.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_up2.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_up3_dn2.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_up3_dn2_polyphase.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_up3_dn2_polyphase_2x2.vhd dpd_v6_0_example_design/src/device/common/hdl/dfe_up3_dn2_polyphase_test.vhd dpd_v6_0_example_design/src/device/common/hdl/dpd_dpram.vhd dpd_v6_0_example_design/src/device/virtex6/ dpd_v6_0_example_design/src/device/virtex6/generic/ dpd_v6_0_example_design/src/device/virtex6/generic/netlist/ dpd_v6_0_example_design/src/device/virtex6/generic/netlist/adc_fifo_buffer_8kx12b.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/fifo_16.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/fifo_32bit.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/fifo_48_192.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/ml605_demo_dlb_complex_mult.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/srx_fifo_dmux.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/up2_245_sharp.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/up3dn2_79taps_2x.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/up3dn2_79taps_parallel_2.ngc dpd_v6_0_example_design/src/device/virtex6/generic/netlist/up3dn2_79taps_parallel_3.ngc dpd_v6_0_example_design/src/device/virtex6/jtag/ dpd_v6_0_example_design/src/device/virtex6/jtag/netlist/ dpd_v6_0_example_design/src/device/virtex6/jtag/netlist/jtagcosim_shmem.ngc dpd_v6_0_example_design/src/device/virtex6/pc_cfr/ dpd_v6_0_example_design/src/device/virtex6/pc_cfr/hdl/ dpd_v6_0_example_design/src/device/virtex6/pc_cfr/hdl/dfe_cfr_wrapper.vhd dpd_v6_0_example_design/src/dpd_v6_0/ dpd_v6_0_example_design/src/dpd_v6_0/debug_if/ dpd_v6_0_example_design/src/dpd_v6_0/debug_if/create_wrapper.pl dpd_v6_0_example_design/src/dpd_v6_0/debug_if/debug_interface.vhd dpd_v6_0_example_design/src/dpd_v6_0/debug_if/dpd_debug_wrapper.vht dpd_v6_0_example_design/src/dpd_v6_0/hdl/ dpd_v6_0_example_design/src/dpd_v6_0/hdl/dpd_cordic_abs.vhd dpd_v6_0_example_design/src/dpd_v6_0/hdl/dpd_dpram.vhd dpd_v6_0_example_design/src/dpd_v6_0/hdl/dpd_qmc.vhd dpd_v6_0_example_design/src/package/ dpd_v6_0_example_design/src/package/hdl/ dpd_v6_0_example_design/src/package/hdl/dfe_base_pkg.vhd dpd_v6_0_example_design/src/package/hdl/dfe_component_pkg.vhd dpd_v6_0_example_design/src/platform/ dpd_v6_0_example_design/src/platform/kc705/ dpd_v6_0_example_design/src/platform/kc705/ddr/ dpd_v6_0_example_design/src/platform/kc705/ddr/hdl/ dpd_v6_0_example_design/src/platform/kc705/ddr/hdl/dfe_kc705_ddr_controller.vhd dpd_v6_0_example_design/src/platform/kc705/ddr/mig_v1_4/ dpd_v6_0_example_design/src/platform/kc705/ddr/mig_v1_4/clocking/ dpd_v6_0_example_design/src/platform/kc705/ddr/mig_v1_4/clocking/clk_ibuf.v dpd_v6_0_example_design/src/platform/kc705/ddr/mig_v1_4/clocking/infrastructure.v dpd_v6_0_example_desig
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