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文件名称:Dual_port_RAM

  • 所属分类：
    Communication
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-01
  • 文件大小：
    629.33kb
  • 已下载：
    0次
  • 提 供 者：
    che****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

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很精彩的双端口RAM应用笔记，对搞单片机、FPGA的都有帮助。-dual_port_ram
相关搜索： fpga VHDL dual-port RAM 双端口ram dual port r 单片机 dualport ram ug dual_port ram Dual-Port R fpga 单片机

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM.gen
Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM.log
Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM.shx
Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM_R0C0.mem
Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM.v
Dual_port_RAM/smartgen/Doul_RAM/Doul_RAM.cxf
Dual_port_RAM/smartgen/Doul_RAM_work.ixf
Dual_port_RAM/smartgen/smartgen.aws
Dual_port_RAM/hdl/ctrl_doul_RAM.v
Dual_port_RAM/hdl/top.v
Dual_port_RAM/hdl/hdlsynchk.tcl
Dual_port_RAM/viewdraw/vf/project.lst
Dual_port_RAM/viewdraw/viewdraw.ini
Dual_port_RAM/simulation/modelsim.ini.sav
Dual_port_RAM/simulation/meminit.dat
Dual_port_RAM/simulation/Doul_RAM_R0C0.mem
Dual_port_RAM/simulation/run.do
Dual_port_RAM/simulation/modelsim.log
Dual_port_RAM/simulation/presynth/_info
Dual_port_RAM/simulation/presynth/@doul_@r@a@m/_primary.vhd
Dual_port_RAM/simulation/presynth/@doul_@r@a@m/verilog.psm
Dual_port_RAM/simulation/presynth/@doul_@r@a@m/_primary.dat
Dual_port_RAM/simulation/presynth/read_wirte_ram/_primary.vhd
Dual_port_RAM/simulation/presynth/read_wirte_ram/verilog.psm
Dual_port_RAM/simulation/presynth/read_wirte_ram/_primary.dat
Dual_port_RAM/simulation/presynth/top/_primary.vhd
Dual_port_RAM/simulation/presynth/top/verilog.psm
Dual_port_RAM/simulation/presynth/top/_primary.dat
Dual_port_RAM/simulation/presynth/stimulus/_primary.vhd
Dual_port_RAM/simulation/presynth/stimulus/verilog.psm
Dual_port_RAM/simulation/presynth/stimulus/_primary.dat
Dual_port_RAM/simulation/presynth/tb_clock_minmax/_primary.vhd
Dual_port_RAM/simulation/presynth/tb_clock_minmax/verilog.psm
Dual_port_RAM/simulation/presynth/tb_clock_minmax/_primary.dat
Dual_port_RAM/simulation/presynth/testbench/_primary.vhd
Dual_port_RAM/simulation/presynth/testbench/verilog.psm
Dual_port_RAM/simulation/presynth/testbench/_primary.dat
Dual_port_RAM/simulation/modelsim.ini
Dual_port_RAM/simulation/vsim.wlf
Dual_port_RAM/simulation/wave.do
Dual_port_RAM/synthesis/Doul_RAM_syn.prj
Dual_port_RAM/synthesis/stdout.log
Dual_port_RAM/synthesis/syntmp/Doul_RAM_flink.htm
Dual_port_RAM/synthesis/syntmp/Doul_RAM_srr.htm
Dual_port_RAM/synthesis/syntmp/Doul_RAM_toc.htm
Dual_port_RAM/synthesis/syntmp/sap.log
Dual_port_RAM/synthesis/syntmp/Doul_RAM.plg
Dual_port_RAM/synthesis/syntmp/Doul_RAM.msg
Dual_port_RAM/synthesis/Doul_RAM.srr
Dual_port_RAM/synthesis/Doul_RAM.htm
Dual_port_RAM/synthesis/Doul_RAM.tlg
Dual_port_RAM/synthesis/Doul_RAM.srs
Dual_port_RAM/synthesis/Doul_RAM.sap
Dual_port_RAM/synthesis/Doul_RAM.fse
Dual_port_RAM/synthesis/Doul_RAM.srd
Dual_port_RAM/synthesis/Doul_RAM.srm
Dual_port_RAM/synthesis/Doul_RAM.map
Dual_port_RAM/synthesis/Doul_RAM.edn
Dual_port_RAM/synthesis/Doul_RAM.sdf
Dual_port_RAM/synthesis/Doul_RAM_sdc.sdc
Dual_port_RAM/synthesis/Doul_RAM.areasrr
Dual_port_RAM/synthesis/Doul_RAM_drc.rpt
Dual_port_RAM/synthesis/Doul_RAM.v
Dual_port_RAM/stimulus/Doul_RAM.hpj
Dual_port_RAM/stimulus/waveperl.log
Dual_port_RAM/stimulus/BtimErrors.log
Dual_port_RAM/stimulus/files_to_build.txt
Dual_port_RAM/stimulus/Doul_RAM.dsk
Dual_port_RAM/stimulus/top.hpj
Dual_port_RAM/stimulus/top_tbench.btim
Dual_port_RAM/stimulus/top_tbench.bk
Dual_port_RAM/stimulus/top.dsk
Dual_port_RAM/stimulus/top_tbench.v
Dual_port_RAM/designer/impl1/Doul_RAM.tcl
Dual_port_RAM/designer/impl1/designer_genhdl.log
Dual_port_RAM/Dual_port_RAM.prj
Dual_port_RAM/simulation/presynth/@doul_@r@a@m
Dual_port_RAM/simulation/presynth/read_wirte_ram
Dual_port_RAM/simulation/presynth/top
Dual_port_RAM/simulation/presynth/stimulus
Dual_port_RAM/simulation/presynth/tb_clock_minmax
Dual_port_RAM/simulation/presynth/testbench
Dual_port_RAM/simulation/presynth/_temp
Dual_port_RAM/designer/impl1/simulation
Dual_port_RAM/smartgen/Doul_RAM
Dual_port_RAM/viewdraw/vf
Dual_port_RAM/viewdraw/sch
Dual_port_RAM/viewdraw/sym
Dual_port_RAM/viewdraw/wir
Dual_port_RAM/simulation/presynth
Dual_port_RAM/synthesis/syntmp
Dual_port_RAM/designer/impl1
Dual_port_RAM/smartgen
Dual_port_RAM/hdl
Dual_port_RAM/viewdraw
Dual_port_RAM/simulation
Dual_port_RAM/synthesis
Dual_port_RAM/stimulus
Dual_port_RAM/designer
Dual_port_RAM/constraint
Dual_port_RAM/component
Dual_port_RAM/coreconsole
Dual_port_RAM/phy_synthesis
Dual_port_RAM

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