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文件名称:debounce_2_Verilog

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    2012-11-06
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    420.38kb
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用VerilogHDL编写的按键消抖程序

分频产生100Hz的按键采样时钟,采样时钟周期为10ms,

按键按下后,产生时间为10ms的低电平信号,即LED亮10m-*Project Name :debounce

*Module Name :debounce

*Target Device :Any Altera FPGA/CPLD Device

*Clkin : 50MHz

*Desisgner : zhaibin

*Date  : 2011-11-18

*Version  : 2.00

*Descriprion :debounce_VerilogHDL
(系统自动生成,下载前可以参看下载内容)

下载文件列表

debounce_2_Verilog/code/debounce.v
debounce_2_Verilog/code
debounce_2_Verilog/db/debounce.(0).cnf.cdb
debounce_2_Verilog/db/debounce.(0).cnf.hdb
debounce_2_Verilog/db/debounce.asm.qmsg
debounce_2_Verilog/db/debounce.asm_labs.ddb
debounce_2_Verilog/db/debounce.cbx.xml
debounce_2_Verilog/db/debounce.cmp.bpm
debounce_2_Verilog/db/debounce.cmp.cdb
debounce_2_Verilog/db/debounce.cmp.ecobp
debounce_2_Verilog/db/debounce.cmp.hdb
debounce_2_Verilog/db/debounce.cmp.kpt
debounce_2_Verilog/db/debounce.cmp.logdb
debounce_2_Verilog/db/debounce.cmp.rdb
debounce_2_Verilog/db/debounce.cmp.tdb
debounce_2_Verilog/db/debounce.cmp0.ddb
debounce_2_Verilog/db/debounce.cmp2.ddb
debounce_2_Verilog/db/debounce.cmp_merge.kpt
debounce_2_Verilog/db/debounce.db_info
debounce_2_Verilog/db/debounce.eco.cdb
debounce_2_Verilog/db/debounce.eds_overflow
debounce_2_Verilog/db/debounce.fit.qmsg
debounce_2_Verilog/db/debounce.hier_info
debounce_2_Verilog/db/debounce.hif
debounce_2_Verilog/db/debounce.lpc.html
debounce_2_Verilog/db/debounce.lpc.rdb
debounce_2_Verilog/db/debounce.lpc.txt
debounce_2_Verilog/db/debounce.map.bpm
debounce_2_Verilog/db/debounce.map.cdb
debounce_2_Verilog/db/debounce.map.ecobp
debounce_2_Verilog/db/debounce.map.hdb
debounce_2_Verilog/db/debounce.map.kpt
debounce_2_Verilog/db/debounce.map.logdb
debounce_2_Verilog/db/debounce.map.qmsg
debounce_2_Verilog/db/debounce.map_bb.cdb
debounce_2_Verilog/db/debounce.map_bb.hdb
debounce_2_Verilog/db/debounce.map_bb.logdb
debounce_2_Verilog/db/debounce.pre_map.cdb
debounce_2_Verilog/db/debounce.pre_map.hdb
debounce_2_Verilog/db/debounce.rtlv.hdb
debounce_2_Verilog/db/debounce.rtlv_sg.cdb
debounce_2_Verilog/db/debounce.rtlv_sg_swap.cdb
debounce_2_Verilog/db/debounce.sgdiff.cdb
debounce_2_Verilog/db/debounce.sgdiff.hdb
debounce_2_Verilog/db/debounce.sim.cvwf
debounce_2_Verilog/db/debounce.sim.hdb
debounce_2_Verilog/db/debounce.sim.qmsg
debounce_2_Verilog/db/debounce.sim.rdb
debounce_2_Verilog/db/debounce.sld_design_entry.sci
debounce_2_Verilog/db/debounce.sld_design_entry_dsc.sci
debounce_2_Verilog/db/debounce.syn_hier_info
debounce_2_Verilog/db/debounce.tan.qmsg
debounce_2_Verilog/db/debounce.tis_db_list.ddb
debounce_2_Verilog/db/debounce.tmw_info
debounce_2_Verilog/db/prev_cmp_debounce.asm.qmsg
debounce_2_Verilog/db/prev_cmp_debounce.fit.qmsg
debounce_2_Verilog/db/prev_cmp_debounce.map.qmsg
debounce_2_Verilog/db/prev_cmp_debounce.qmsg
debounce_2_Verilog/db/prev_cmp_debounce.sim.qmsg
debounce_2_Verilog/db/prev_cmp_debounce.tan.qmsg
debounce_2_Verilog/db/wed.wsf
debounce_2_Verilog/db
debounce_2_Verilog/debounce.asm.rpt
debounce_2_Verilog/debounce.done
debounce_2_Verilog/debounce.dpf
debounce_2_Verilog/debounce.fit.rpt
debounce_2_Verilog/debounce.fit.smsg
debounce_2_Verilog/debounce.fit.summary
debounce_2_Verilog/debounce.flow.rpt
debounce_2_Verilog/debounce.map.rpt
debounce_2_Verilog/debounce.map.summary
debounce_2_Verilog/debounce.pin
debounce_2_Verilog/debounce.pof
debounce_2_Verilog/debounce.qpf
debounce_2_Verilog/debounce.qsf
debounce_2_Verilog/debounce.qws
debounce_2_Verilog/debounce.sim.rpt
debounce_2_Verilog/debounce.sof
debounce_2_Verilog/debounce.tan.rpt
debounce_2_Verilog/debounce.tan.summary
debounce_2_Verilog/debounce.v.bak
debounce_2_Verilog/debounce.vwf
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.atm
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.dfp
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.hdbx
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.kpt
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.logdb
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.cmp.rcf
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.map.atm
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.map.dpi
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.map.hdbx
debounce_2_Verilog/incremental_db/compiled_partitions/debounce.root_partition.map.kpt
debounce_2_Verilog/incremental_db/compiled_partitions
debounce_2_Verilog/incremental_db/README
debounce_2_Verilog/incremental_db
debounce_2_Verilog

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