搜索资源列表
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
uart(Verilog)
- uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件
cuart
- verilog编写的全功能串口-verilog programme of serial port
rs232的verilog程序
- 串口的一个verilog程序。
UART.rar
- 主芯片：Actel的FPGA030,Verilog语言,串口发送和接收的例程，开发环境：LiberoIDE 8.5,The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
my_232
- verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
zigbee_sensor
- ZigBee无线模块实验.rar；基于FPGA-2C35核心；博创实验箱平台。 在quartusII里面添加uart核，利用串口与主控制机相通信，获取从控制机上传感器的的温度、湿度、光敏电阻、热敏电阻等信息（其中主控制机与从控制机是通过zigbee协议通信） -ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear qua
UART
- 使用verilog实现串口通信功能，modesim仿真成功(Using Verilog to achieve serial communication function, modesim simulation success)
rx_tx_interface_demo
- 精简的verilong串口通信源码，带通信自定义模块(Streamlined verilong serial communication source code, with communication custom module)
uart_ip
- 实现串口通信模块设置，包括频率分频、波特率产生、接口时序要求(Implementation of serial communication module settings, including frequency division, baud rate generation, interface timing requirements)
Chuankou
- 实现8位串口的接收和发送模块，将串口接收和发送模块分成了几个小模块进行设计。方便之后的bug的修改。(Receiving and sending module of 8 bit serial port)
No.201710061347=UART_Verilog
- 1.硬件平台： FPGA； 2.编程语言： Verilog； 3.串口通信RS232的Verilog实现版本；(1. hardware platform: FPGA; 2. programming language: Verilog; The Verilog implementation version of 3. serial port communication RS232;)
uart
- 串口发送接收模块，verilog语言，可用来做hdl设计的仿真(used for test for Uart interface in FPGA)
07_uart_test
- 黑金FPGA开发板实现串口Uart通信的verilog代码(Serial Uart communication)
FPAG UART Verilog
- FPGA实现URAT，实现异步串口收发控制(FPGA implements URAT to realize asynchronous serial port and transceiver control)
tx_interface_project
- 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
uart
- 实现串口的收发，可以稳定的运行，经过测试，可以完全应用于项目中。(The implementation of the serial port and transceiver, can run stable)
Tx
- 利用verilog实现串口发送，每次按键一次发送一次数据，按键模块进行了消抖处理(Using Verilog to realize serial port sending. Each button sends one data at a time, and the key module performs buffeting processing.)
fpga 实现 串口通信
- 串口通信，可以任意修改波特率， 亲自验证过，通信可靠，采用verilog HDL语言编写，代码包含注解