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JPEG2000_9_7_002.pdf
- 基于实数的二进制表示法，把CDF(Cohen，Daubechies and Feauveau)9／7双正交小波基的提升系数化为二进制，采用简单的移位一加操作代替结构复杂的浮点乘法器，从而实现了JPEG2000中9／7离散小波变换的定点计算．相对于浮点计算法，移位一加操作最大的优点是计算简单，特别易于超大规模集成电路实现，因而使硬件实时处理图像信号成为可能．实验仿真结果表明：在低压缩比的情况下，用移位一加操作重构的图像，其峰值信噪比(PSNR)只比浮点法低0．10 dB，当压缩比增大时，其PSNR
5438mpy
- msp430单片机最新的产品MSP430F5438内部硬件乘法器的操作的示例程序-MSP430 Product latest single-chip hardware multiplier MSP430F5438 internal operation of the sample programs
VHDL_exmple
- VHDL编程一百例，包括加法器、乘法器、移位寄存器、奇偶校验器等。pdf格式的，仅供学习使用-VHDL Programming 100 cases, including the adder, multiplier, shift register, parity, etc.. pdf format, for learning to use
ff_mul
- 伽勒华域乘法器用于RS编码中，用verilogHDL语言实现-Galle Hua domain multiplier for RS encoding, the implementation language used verilogHDL
chengfaqi(xuniyiqi)
- 一个以LABVIEW环境开发的乘法器程序后面板和前面板-LABVIEW environment for the development of a multiplier after the panel and front panel
ex
- 用HDPLD实现的高速并行乘法器，其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
Boothmultiplier
- 布斯乘法器的语言描述功能违反外 暗暗达到-Booth multiplier described in the language
Mars_EP1C6F_fundemantal_demo
- FPGA 开发板源码。芯片为Mars EP1C6F.VHDL语言。可实现一些基本的功能。如乘法器、加法器、多路选择器等。-FPGA development board source. Chips for the Mars EP1C6F.VHDL language. Can achieve some of the basic functions. Such as multiplier, adder, such as MUX.
multipilier8x8_spice
- 用spice描述的8x8改进Booth码加wallance压缩的乘法器，并且进行了优化，时间性能相当高-the improved Booth coding plus wallance multipliler ,I have optimized it which gained short time and performance,it is descr ipted by spice
Multiplexer
- 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
multi
- 实现了三种乘法器，可以进行性能比较，比较有较之-multi
GF_MUL
- Galois域乘法器的Verilog源码 广泛用于信道编码、计算机代数及椭圆曲线加密等-Galois field multipliers are widely used in the Verilog source channel coding, computer algebra and elliptic curve encryption
EPM1270_multiplier
- VHDL 乘法器 源代码，很好的VHDL 入门学习例程序-Multiplier VHDL source code, a good learning example VHDL entry procedures
0
- 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
DDS-baseddesignofthesinusoidalsignalgenerator
- 本设计采用AT89552单片机，辅以必要的模拟电路，实现了一个基于直接数字频率合成技术(DDS)的正弦谊号发生器。设计中采用DDS芯片AD9850产生频率1KHZ~10MHZ范围内正弦波，采用功放AD811控制输出电压幅度， 由单片机AT89S52控制调节步进频率1HZ。在此基础上，用模拟乘法器MC1496实现了正弦调制信号频率为1KHZ的模拟相度调制信号；用FPGA芯片产生二进制NRZ码,与AD9850结合实现相移键控PSK、幅移键控ASK、频移镇键FSK。-AT89552 the singl
adder
- 采用加法树流水线乘法构造八位乘法器，并分析设计的性能和结果在时钟节拍上落后的影响因素。 -Multiplication using adder tree structure line 8 multiplier, the design and analysis of the results of the performance and beat the clock on the impact of the factors behind.
erweiDCT
- 用 FPGA实现了二维离散余弦变换和逆变换，结构设计采用行列分解法，乘法器采用移位求和的方法实现，并且采用流水线结构设计，提高处理核的性能-Using FPGA to achieve the two-dimensional discrete cosine transform and inverse transform, the structural design of the use of the ranks of decomposition, the sum of multipliers us
Multiplier
- 用VHDL语言仿真乘法器设计。能够实现一般乘法运算。-Multiplier using VHDL language design simulation. Multiplication can be achieved in general.
cfq8
- VHDL语言编写8位乘法器非常实用语言绝对正确经过仿真的-VHDL language is very practical 8-bit multiplier is absolutely correct language after simulation
3-bit_multiplier
- 用ASM原理做二進位3-BIT乘法的乘法器，內附範例的輸入檔。-ASM to do with the principle of binary multiplication of 3-BIT multiplier, the input file containing a sample.