搜索资源列表
Verilog_EX
- 移位乘法器/流水线乘法器，流水线结构的基本应用-Pipelined multiplier
8bit-multiplier
- 8位二进制数乘法器VHDL实现8位二进制数乘法器设计，乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全0相加，直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of
multi_CX
- 实现8*8串行乘法器的verilog源代码，经过调试的哦！-8* 8 serial multiplier verilog source code, after debugging Oh!
multi_4bits_pipelining
- 实现4*4流水线乘法器的verilog源代码，在FPGA板上运行-4* 4 pipelined multiplier verilog source code, running on the FPGA board
mul
- 带符号数的乘法器，包含补码与原码之间的转换-failed to translate
multiplier_ip
- 基于IP核的乘法器设计，完整的设计工程文件在multiplier_ip文件夹下-IP-based core multiplier design, complete design engineering file multiplier_ip file folder
multiply_shift_add
- 基于移位相加运算的乘法器设计，完整的设计工程文件在multiply_shift_add文件夹下-Multiplier design based on shift and add operations, complete design engineering file multiply_shift_add file folder
Chapter16-Multiplier
- 书籍《精通Verilog HDL语言编程》中第16章的程序实例代码，是关于常用乘法器的设计的，对于初学者有一定的帮助-Book "Proficient in Verilog HDL language programming" in Chapter 16 of the procedure code, the common multiplier designed for beginners will certainly help
16-bit-parallel-mult
- 16位并行乘法器， 由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
coding
- 数字通信系统设计上机实验题，二分频，全加器，乘法器，四选一选择器-Digital communication system design on the experimental questions, divide, full adders, multipliers, four elected a selector
VHDL_book2
- add4a：4位加法器的设计 add8a：8位加法器的设计 subtract：4位减法器的设计 addsub： 4位加法器/减法器的设计 shift4：移位寄存器的设计 mult4：乘法器设计 div8：除法器设计 alu4：算术逻辑单元ALU设计-add4a: 4-bit adder design add8a: 8 bit adder design subtract: 4-bit subtraction Design addsub: 4-bit ad
vhdl1
- 该程序实现了运用VHDL实现数字音频滤波，同时在FIR 滤波过程中减少了加法器和乘法器使用数量，大大减小了内存-The program implements the use of VHDL digital audio filtering, while in the FIR filtering process to reduce the number of adders and multipliers used, which greatly reduces the memory
qt
- FPGA软核IP生成工具.保存设置,生成5种常见简单软核,计数器,乘法器,存储器-FPGA-based soft IP core generation tool
carry_save_mult
- 常用乘法器设计 样例程序-Common Multiplier sample program
ff_mul
- 伽罗华域GF（q）乘法器设计-Galois field GF (q) Multiplier
A
- 四位二进制乘法器的设计，通过设计我们可以掌握计算机的乘法运算方法，了解Maxpuls软件-Four binary multiplier design, we can master the computer through the design multiplication methods to understand Maxpuls Software
16bits_multiplier
- 这是一个有符号的16位乘法器的设计，包含详细的设计报告和全部的verilog代码。乘法器采用booth编码，4-2压缩，超前进位结构-This is a signed 16-bit multiplier design, detailed design reports and contains all of the verilog code. Multiplier using booth encoding ,4-2 compression, lookahead structure
module-multiplier
- 用vhdl编程，实现了一个2^N+1模乘法器，经验证，设计结果完全正确-use the vhdl language to design a module 2^n+1 multiplier
multi8X8
- 基于vhdl的8为乘法器，移位相加原理，使用VHDL语言-Based on the multiplier vhdl 8, displacement add principle, the use of VHDL language
EX4
- 基于FPGA的16位乘法器，入门的可以好好看看。-FPGA-based 16-bit multiplier, getting started can be a good look.