搜索资源列表
ARITHMETIC
- 算术乘法器，这是我自己设计的算术乘法器，是用VHDL语言设计的，希望对大家有帮助-Arithmetic multiplier, this is my own design arithmetic multiplier, is designed with VHDL language, and they hope to help everyone
multiplier
- 乘法器的verilog工程文件，可以进行仿真实验，有详细解释，适合初学者学习参考。-Multiplier verilog project file, can be simulated, with detailed explanations, suitable for beginners to learn.
mux16
- 在该实验中就是要利用时序逻辑设计方法来设计一个16 位乘法器-In this experiment is to use sequential logic design method to design a 16-bit multiplier
wallace_tree
- 华莱士树的硬件实现，多用于乘法器的加法运算部分-Wallace tree hardware implementation, used for the multiplier adder portion
Multiplier
- 乘法器课程报告，华莱士树算法硬件实现，讲解详细-Multiplier course reports, Wallace tree algorithm implemented in hardware
HighSpeedParallelMultiple
- quartus II 下VHDL实现快速乘法器-quartus II VHDL High Speed Parallel Multiple
mult
- verilog编写的8x16常变量乘法器，可用quartus仿真-verilog prepared 8x16 often variable multiplier, available quartus simulation
A-C8V4
- 淘宝畅销FPGA开发板的A-C8V4 电路图及例子 9实验九：利用语言实现3-8译码器 10实验十：利用语言实现按键和数码管显示 11实验十一：利用语言实现乘法器数码管显示 …… 18实验十八：利用语言实现蜂鸣器唱歌 23实验二十三：利用语言实现LCD1602显示 24实验二十四：利用语言实现LCD12864显示汉字 25实验二十五：利用程序实现串口RS232与电脑通信 28实验二十八：利用程序实现VGA显示RGB彩条信号 31实验三十一：利用程序实
mux16
- 利用FPGA时序逻辑设计16位乘法器。利用时序逻辑设计可以使整体设计具备流水线结构-Sequential logic design using FPGA multiplier 16. Sequential logic design allows the use of the overall design with pipeline structure
chengfa
- 实现两个数的相乘，安卓乘法器，基于eclipse开发安卓应用-Achieved by multiplying two numbers
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
16_bit
- 采用boot算法的16位乘法器,速度较快，可以试下哈-Boot algorithm using 16-bit multiplier, faster, you can try under the Kazakhstan
Common-multiplier-design
- 常用乘法器设计，用FPGA能实现，值得下载。-Common multiplier design, FPGA can achieve, it is worth downloading.
GF-(q)-multiplier-design
- 伽罗华域GF（q）乘法器设计,FPGA实现-Galois field GF (q) multiplier design, FPGA realization
verific_evaluation
- 这是一个比较大的数字逻辑电路的verilog代码，具有版权保护，可以实现多输入乘法器。-This is a relatively large verilog code digital logic circuits, with copyright protection, you can achieve multiple-input multiplier.
FPGA-Implementation
- 20×18位符号定点乘法器的FPGA实现-2018 fixed-point multiplier symbol FPGA Implementation
method1
- 脉动乘法器的HDL实现，包括DC、Astro跑版图-using HDL implements GM multiplier，including src，DC，and Adtro layout
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
cheng
- 开放式实验，CPU的设计，乘法器实验，简单乘法器-Open experiment, CPU design, the multiplier experiment, a simple multiplier
multiply_vhdl
- 用VHDL语言设计一款带进位的5位乘法器。-Design with VHDL into a 5-bit multiplier.