搜索资源列表
mul
- 乘法器vhdl程序,主要是 修正后的乘法器，希望对大家有帮助-study the program of vhdl for multiplier
32bitvhdl
- 基于硬件描述语言的通过加法器实现的32位乘法器-Hardware descr iption language implemented by the adder 32 of the multiplier
ChengFaQi_mux16
- 实现16位乘法器 并有modelsim仿真文件-The realization of the 16 bit multiplier and Modelsim simulation file!!!!!!!!!!!!!!!!!!!!!!!!
booth-mutiplier
- booth乘法器的verilog实现及仿真。 内含verilog源码和modelisim仿真源码，清晰的实现了硬件乘法器，代码注释清晰-booth multiplier verilog verilog implementation and simulation contains the source code and modelisim simulation code, clear notes
32FIRVHDL
- 基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 -32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
32bit-multiplier-verilog
- 这是一个32位乘法器，是用verilog写的，比较详细-32*32 multiplier
MPY
- MSP430F1XX系列单片机 内部硬件乘法器 MPY应用-MSP430F1XX MPY
Multiply8-6
- FPGA verilog用移位相加的方式来实现8位的乘法器-FPGA verilog With shift and add a way to achieve 8 multiplier
some-kinds-multiple-Verilog
- 几种常见的乘法器的verilog代码，已经试过可用-some kinds of multiplier for verilog, it is useful
ParallelSerialMult
- 用verilog代码实现了 并行线性序列乘法器，流水线技术实现了乘法操作-Verilog code using a linear sequence of parallel multipliers, pipeline technology to achieve a multiplication operation
9_6
- 介绍一个包含编辑框控件的“乘法器”程序，使用者在“乘数”或者“被乘数”编辑框输入数字的时候，程序可以随时计算乘法的结果-Introduction of an edit control that contains " multipliers" program, the user " multiplier" or " multiplicand" edit box enter a number, the program can be readily
mux_16
- 16位乘法器的功能主要体现7个部分进行16*16的乘法计算但其设计原理可用来计算更多位的乘法计算。-But its design principles can be used to calculate more multiplication calculation 16 bit multiplier function mainly embodies 7 parts of 16*16 multiplication.
multiplier.v
- 依旧是自己写的一个8*8的乘法器的verilog代码，所以请大家下载，-Verilog still write their own code of an 8* 8 multiplier, so please download, thank you
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
8bit_multiplier
- 8bit 无符号串联乘法器，由状态机实现，用相加与移位实现乘法功能。-Unsigned 8bit serial multiplier, the state machine implementation, realized by adding the shift multiplication function.
chengfaqi
- 基于51单片机的乘法器，含proteus仿真，用keilC编译的，代码详细，含有注释，望点个赞，谢谢，头文件全，方便移植。-Based on 51 single-chip multiplier, with proteus simulation, using keilC compiled code in detail, contains notes, looking like a point
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
multiplying-unit
- fpga verilog入门经典系列完整版，下载即用:乘法器-fpga verilog multiply
mult_piped_8x8_2sC_h1
- 這是由我自己寫的8位元乘法器,雖然不是最好的但是希望能提供同學們課業上的好幫助-It was written by my own 8 yuan multiplier, though not the best but hope to provide better help students on academic