搜索资源列表
Experiment01
- FPGA源码，初学者使用，时序程序分析，整数乘法器-FPGA source code, for beginners to use, timing program analysis，Integer multiplier
DDC-based-on-CORDIC-.pdf
- FPGA平台上基于CORDIC架构实现DDC的方案，将传统的本振和混频两个单元合在一起完成，省去了查找表和硬件乘法器资源-Implementation of DDC CORDIC architecture scheme based on the FPGA platform, the traditional local oscillator and mixer two units together to complete, eliminating the look-up table and har
multer
- 16*16位的乘法器，用booth编码，采用Wallace树结构，用超前进位加法器。-booth encoded multiplier
Booth2-multiplier
- 一个18bit乘以18bit的Booth2编码的乘法器，已验证通过-A 18bit*18bit booth2 mutiplixer
systolic_mul_D8_M193
- 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
matrix
- 设计一个简单的2x2阶的矩阵乘法器, A，B 为2*2矩阵 求：C=A*B-Order to design a simple 2x2 matrix multiplier, A, B 2* 2 matrix: C = A* B
complexMul
- 复数乘法器，利用ISE里的float IP核，实现了32位复数的乘法-Complex multiplier, using the ISE in the float IP core to achieve the 32 complex multiplications
adder_sub_mul
- 加法器，减法器，乘法器，超前进位，一位拓展成四位-adder and subber are written by the language of VerilogHDL one bit to four bits.
mul16
- 16位二进制数移位乘法器的实现,使用Verilog HDL实现-The realization of the 16 bit binary number shifting multiplier, use Verilog HDL to implement
booth_multiplie_module
- 利用verilog实现的Booth算法乘法器，对想学习乘法器的将会有很大的帮助.-Booth algorithm verilog realization use multipliers, the multiplier will want to learn a great help.
4booth_multiplie_module_2
- 采用Verilog对Booth算法乘法器的改进，对想学习乘法器的会有很大的帮助。-Improved algorithm using Verilog Booth multiplier, multiplier want to learn to have a lot of help.
5lut_multiplier_module
- 利用Verilog编写的基于Quartersquare的查表法乘法器，对想学习乘法器的将会有很大的帮助-Use Verilog prepared Quartersquare the look-up table based multiplier multiplier will want to learn a great help
6modified_booth_multiplier_module
- 利用Verilog编写的ModifiedBooth乘法器，对想学习乘法器的将会有很大的帮助-Use Verilog prepared ModifiedBooth multiplier, multiplier will want to learn a great help
jiajianchengchu
- 4.移位相加式十进制硬件乘法器电路， 要求：输入两个1位十进制数，利用移位相加法计算它们的乘积，显示乘数、被乘数和积。-The shift and add type decimal hardware multiplier circuit, Requirements: Enter both a decimal number, and calculate their product using a shift-add method, display multiplier, multiplic
project
- hspice编写的4位乘法器，运用了wallace-tree的方法-hspice muler
my_multiplier
- 一个VHDL编的简单乘法器，基本原理设计如下图所示: 将两个操作数分别以串行和并行模式输入到乘法器的输入端, 用串行输入操作数的每一位依次去乘并行输入的操作数, 每次的结果称之为部分积, 将每次相乘得到的部分积加到累加器里, 形成部分和, 部分和在与下一个部分积相加前要进行移位操作。-A simple multiplier VHDL series, the basic principles of design as follows: two operands, respectively, ser
mul
- 使用Verilog实现的原码4位数的移位乘法器-Using Verilog to realize the original code 4 bit shift multiplier
ad5544
- 模数乘法器AD5544的Verilog源程序，已在项目中验证了其可行。-Verilog source AD5544 analog multiplier, and have verified its feasibility in the project.
code
- 基于FPGA的乘法器译码器程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-FPGA multiplier based procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
chengfaqi
- 乘法器设计，仿真文件也包含在其中，供学习使用-Multiplier，you can use it