搜索资源列表
mult
- 一个4位二进制数乘法器，基于vhdl实现的，8位输出二进制-4 binary multiplier implemented based vhdl
chengfaqi
- 完成该3位3位的乘法器,把乘法问题转化为逻辑“与”运算和加法运算。-The completion of the 3 3 bit multipliers, the multiplication problem is transformed into a logic and operation and the addition operation.
project16
- 九九乘法器，对ROM的编写，最终实现在试验箱的数码管上分别显示乘数，被乘数，积-Jiujiushengfa device for the preparation of ROM, and ultimately show the multiplier, multiplicand, respectively, in the chamber of the digital control, product
32bit_multiply
- 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementat
eetop.cn_Booth_mutipler_v2
- 新型32位booth乘法器的实现,使用verilog的一种新型乘法器改进实现-The new 32 booth multiplier implementations
different_multiplier
- 比较了不同设计方法下的乘法器性能，给出了计算公式-Compare the performance of different design methods multiplier under the given formulas
chengfaqi
- 利用51单片机和按键实现乘法器的功能，按键所按数值会在串口中显示出来，并且能在串口中得到作乘法之后的结果-Use SCM and realize multiplier function keys, press the numeric keys are displayed in the serial port, and can be obtained as a result of the multiplication of the serial ports later
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
assignment
- 4*4乘法器，分层化，可扩展，含仿真结果，quartus12.1可用。 -4* 4 multiplier, hierarchical struction, including simulation results, quartus12.1 available.
cmp42
- 用于乘法器设计，8位Booth译码乘法器，4-2压缩结构，加速乘法运算速度-Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate
book3e
- 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
chengfaqi
- 数字电路中实现八位二进制乘法器的VHDL代码-Digital Circuit achieves eight binary multiplier VHCDL code
chengfaqi
- 16位的原码两位乘法器，实现原码两位乘，经试验可以使用-16 of the original code two multiplier, two implementation source code
fwdfwfft
- 4位的16点fft，ccmul为复数乘法器，bfproc为蝶形运算器，输出的结果为四位，每一级都要进行round操作。-4 16-point fft, ccmul for complex multiplier, bfproc for the butterfly operation, a result output is four, each stage should be carried out round operation.
Booth2_final
- 该文件是booth乘法器的verilog源代码，经过最终的仿真，可以直接运行-This file is booth multiplier verilog code, after the final simulation, can be directly run
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
SOC_Code
- 加法器，原码补码乘法器，ROM设计，PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail
MSP430x261x_MPY
- MSP430x261x 硬件乘法器配置程序-MSP430x261x hardware multiplier configuration program
Galois-field-GF-(q)-.
- 伽罗华域GF（q）乘法器设计在FPGA板上的应用-Galois field GF (q) application of multiplier design on the FPGA board.
cfq[1]
- 简单乘法器调制信号频谱分析，简单入门教程-Simple multiplier modulation signal spectrum analysis