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Timing1111_Symcronization
- 使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过-Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by
Gardner
- 关于位同步算法的gardner一篇不错的pdf文档 虽然简单 说的很清楚明白-pdf about gardner for timing synchronization,thought it is simple but it is very usefull
bitsynchronization
- 位同步源代码，是关于MATLAB的，很好的，并且具体有调制解调的功能！-Bit synchronization source code on MATLAB, very good, and the specific modulation and demodulation functions
zaibo
- 16QAM解调算法，载波同步和位同步算法-16QAM demodulation algorithm
timing_syn_Gardner
- 实现了DQPSK下用Gardner算法实现位同步，并对信噪比、余弦滚降因子的影响加以讨论-achieve symbol synchronous by Gardner in the condition of DQPSK
CAN-basic
- 恒润对于CAN通信原理、驱动、数据帧、位同步、波特率计算等的详细描述。汽车CAN通信设计必备资料。-Hengrun for CAN communication principle, drive, data frame synchronization bits, baud rate calculation such as a detailed descr iption of Automotive CAN communication design essential information.
weitongbu
- 基于fpga的位同步信号提取仿真 使用vhdl语言 quartus-To use vhdl language quartus fpga bit synchronization signal extraction-based simulation
bitsynchro
- 自己写的位同步实验程序参考，该算法需要发送和接收方的频率比较稳定时，可以很快地达到位同步，且十分稳定。位同步是通信技术的基础之一，希望对大家学习有所帮助。-The program is a reference used for bitsynchro writed by myself.When the both send s and receive s frequency are stable,the program can reach bitsynchro fastly.
wei
- 位同步的verilog实现，利用窄脉冲来延迟或提前相位达到同步-Verilog achieve bit synchronization using narrow pulses reach synchronization to delay or advance phase
4wei-ji-shu-qi
- 4位同步二进制加法计数器的工作原理是指当时钟信号clk的上升沿到来时，且复位信号clr低电平有效时，就把计数器的状态清0。 在clr复位信号无效（即此时高电平有效）的前提下，当clk的上升沿到来时，如果计数器原态是15，计数器回到0态，否则计数器的状态将加1. -4 synchronous binary adder counter works by the rising edge of the clock signal clk, and the reset signal CLR acti
haishiweixingtufaxinhao
- 是一篇关于基于FPGA海事卫星突发信号位同步的文章，希望对大家有用-One based on FPGA maritime satellite burst signal bit synchronization article, we want to
basys2
- BASYS2 board,FPGA，实现M12序列的生成并加在低频二进制信号上（输入信号），之后实现了位同步提取。-BASYS2 board, FPGA, to achieve M12 sequence generation and added to the low-frequency binary signal (input signal), and then to achieve the bit synchronization extraction.
F161xb8
- 模块名称：4位同步计数器模块 功能描述：完成4位同步计数器的功能-Module Name: 4 Synchronous Counter Module Descr iption: Complete four synchronous counter function
gardner_test
- 无线通信中接收机的位同步，采用的gardner算法实现的verilog程序，需要自己综合编译-Wireless communication receiver bit synchronization algorithm used gardner the verilog program needs its own comprehensive compilation
fdd-LINK
- FDD链路的仿真使用的是KA波段，其中在接收端涉及到多种算法（位同步算法，DD算法等）-FDD link simulation using KA band
CT8022_program
- 此程序先对CT8022进行初始化设置，设置其工作在G.723.1压缩语音数据模式，PCM3500工作在主模式，CT8022工作在从模式，帧同步信号8kHz,位同步信号128kHz，16bitCODEC采集模拟语音信号后传给CT8022，CT8022将压缩后的数据通过无线模块传PC，PC通过串口调试助手接收数据-this program is made for voice compression device CT8022,and CT8022 is working in the G.723.1
Bitsynchronizationclockprogramdesign
- 一种新型位同步时钟提取方案以及实现。基于的是fpga。-A new bit synchronization clock extraction programs and implementation. Based on the fpga.
eight
- 八位同步寄存器（检测时钟上升沿，一个接受复位信号，八位输入赋给八位输出）-eight bit registered
bit_synchronize
- fpga开发的位同步处理模块，能够实现功能并实现良好的效果-fpga developed bit synchronization processing module to achieve the function and achieve good results
zhen1
- 本文设计的数字分接器是由帧同步提取模块、位同步提取模块、帧同步移位和时序信号恢复模块、分路器模块、串/并转换电路模块五部分组成-Digital tapping machine is designed in this paper by the frame synchronization extraction module, a synchronous extraction module, the displacement of frame synchronization and timing si