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ex15
- 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
ADDER_8BIT_FOR_BCD
- 基于FPGA的由两个四位全加器合成的八位全加器 -Based on the synthesis of two four eight full adder full adder FPGA
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
adder8
- 8位全加器，Verilog硬件语言源代码。最基础的加法器。-8-bit carry-ripple adder， the basic adder。Achieved by verilog source code.
EDA
- 1.八进制计数器 2.八位右移寄存器 3.八位右移寄存器（并行输入串行输出） 4.半加 5.半加器 6.半减器 7.两数比较器 8.三数比较器 9.D触发器 10.T触发器 11.JK1触发器 12.JK触发器 13.三位全加器 14.SR触发器 15.T1触发器 16.三太门 17.有D触发器构成的6位2进制计数器 18.带同步置数的7进制减法计数器（6位右移寄存器） 19.二十四进制双向计数器 20.二选一 21
ex15
- 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
adder4
- 使用层次化建模的方法再quartus下实现的4位全加器。包括半加器，一位全加器和四位全加器，并进行了仿真。-This file is used for learners to learn verilog.
quanjia
- 一位全加器 一位全加器 -A full adder a full adder a full adder a full adder
add_verilog
- 2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过-Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output
quanjiaqi
- 改程序是利用LabvIEW实现简单的全加器，该程序可用于全加器的显示，以及原理说明！-LabvIEW reform program is the use of simple full adder, the program can be used to display the full adder and the principle that!
a
- VHDL编写的一个简单的8位全加器，提供分享-VHDL prepared a simple 8-bit full adder, providing shared
LAB3_1
- 一个八位加法器，利用四个全加器组成，并兼有溢出提示功能-An eight adder using four full adder composed, and both spill prompts
adder5
- 5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。-5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
FA
- 使用VERILOG實現全加器的設計,並附上TB供測試-Use VERILOG achieve full adder design, together with a test for TB
f_adder
- 利用VHDL的语言，实现考虑进位的全加器，该程序带中的加法器带有使能端，可以更好地实现所需功能。-Using VHDL language to achieve considering the carry bit full adder, the program with the adder with Enable, can better achieve the desired function.
exp5
- 用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full a
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计，了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
adder2
- 全加器的VHDL数据流描述，提供VHDL代码 可以用Quartus 和MAX PLUS-full adder
CH2
- SystemC的源代码。都测试.这个是关于全加器的设计-SystemC code