搜索资源列表
counter_four
- 模拟了半加器和全加器的vhdl语言源码。-model half add and full add mechine vhdl code
myeda
- eda的程序集，有1位全加器，移位寄存器，计数器，等等的设计-failed to translate
edashiyanbaogao_fzu
- 福州大学07级eda实验报告。。。一共八九份 包含实验指导书 实验一 利用原理图输入法设计4位全加器 一、实验目的： 掌握利用原理图输入法设计简单组合电路的方法，掌握MAX+plusII的层次化设计方法。通过一个4位全加器的设计，熟悉用EDA软件进行电路设计的详细流程。 -07 eda, Fuzhou University lab reports. . . A total of 89 experimental instructions were included experi
edashiyan
- 一个简易的带进位的全加器实现，希望能对大家有益-Into place a simple full adder implementation, hope it' ll be useful
fulladder
- 由四位全加器通过元件例化语句设计成十六位的全加器-By four full adder component instantiated by statements designed 16 of the full adder
4weiquanjia
- 用VHDL写的4位全加器,5.1版本编写的-Use VHDL to write four full adder, 5.1 version of the written
fadder32
- 短代码实现32位全加器，带经Quartus II9.1编程测试全部文件-Short code to achieve 32-bit full adder, with programming tested by the Quartus II9.1 all documents
quanjiaqi
- 建立了基于matlab语言的四位全加器仿真模型，通过了系统验证。-Matlab language is established based on four full adder simulation model, verified by the system.
EDA1
- 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
adder
- 一位全加器,使用绘图方式,将2个半加器制成符号,供全加器调用,组合成全加器,方法简单易行,通过验证.-A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified.
VHDL
- 译码器。半加器，全加器。。。包括源程序和仿真波形-Decoder. Half adder, full adder. . . Including the source and the simulation waveform
07401200310
- VHDL原程序包括译码器，半加器，全加器-VHDL program, including the original decoder, the half adder, full adder
adder4
- 此源代码是基于Verilog语言的4 位全加器，4 位计数器、 4 位全加器的仿真程序、4 位计数器的仿真程序是用EDA语言描述4 位全加器，有广泛的应用。-The Verilog language source code is based on the 4-bit full adder, 4 bit counter, 4-bit full adder simulation program, 4-bit counter of the simulation program is to use la
ADD6
- 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to ac
full_adder
- 通过运用quartusii运用vhdl语言描述一个全加器的设计程序-Vhdl language through the use of quartusii used to describe a full adder design process
alu
- 实现五位加法器功能，还有ALU的程序模块！同时有四位全加器的功能模块！-Adder to achieve five functions, as well as program modules ALU! At the same time there are four full-adder modules!
shiyan3
- 利用文本编辑器和VHDL语言设计一个半加器和或门，将其定义成Symbol图元，在图形编辑器中利用这些Symbol将其设计成一个全加器。下载到CPLD芯片中，接入输入电平信号和输出LED显示器。还有一个4-16译码器的VHDl程序-adder 4-16
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
QUANJIAQI
- 是一用maxplusii 做出来的全加器的完整的ppt非常的详细 -Is made out by maxplusii complete full adder is detailed ppt
full_adder
- 用verilog在半加器的基础上实现了全加器，方法简单巧妙，对于FPGA入门学习很有帮助-In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter