搜索资源列表
waterled_2group
- LED0--LED11,由LED0 LED1开始循环亮,2个灯为一组,每1秒换一组灯亮,这里用的时钟为50MHZ,因此需要外加一个分频器进行分频- LED0- LED11, from the beginning of the loop LED0 LED1 light, two lights as a group, every 1 second for a group of lights, where the clock used for 50MHZ, plus a divider so the
clk_divide
- 实现了一个通用分频器,可以实现任何分频的程序-To achieve a common divider, can achieve any frequency of the procedure
RTC
- RTC 实时时钟,主要用于实现长时间计时。模块包括可选8:1 分频器,一个定时器T14,及一个32 位RTC 计数器。本例程介绍RTC的DAVE配置以及KEIL的编程指导-RTC Real Time Clock, mainly used to achieve a long time. Module includes an optional 8:1 divider, a timer T14, and a 32-bit RTC counter. The routine introduction of
fenpinpi
- quartusii软件仿真实验代码 分频器-quartusii software simulation code divider
20080108103305384
- 本系统是采用EDA技术设计的一个简易的八音符电子琴和音乐发生器,该系统基于计算机中时钟分频器的原理,采用自顶向下的设计方法来实现,它可以通过按键输入来控制音响。系统由乐曲自动演奏模块、乐器演示模块琴/乐功能选择模块、音调发生模块和数控分频模块五个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计,然后进行编程、时序仿真、整合。本系统功能比较齐全,有一定的使用价值.-The system is designed using EDA technology with a simple ei
digital-frequency
- 数字频率计 采用Verilog语言编写,分为8个模块,分别是计数器,门控,分频,寄存器,多路选择,动态位选择,BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
music
- 功能描述:向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调,该实验通过设计一个状态机和分频器使蜂鸣器发出"多来咪发梭拉西多"的音调。(VHDL)-Function Descr iption: to the buzzer to send a certain frequency square wave can make the appropriate buzzer tone, the experiment by designing a state machine and the divider
fenpinqi
- 利用microwave office实现分频器的实验框图及性能分析-Achieved using microwave office divider block diagram and performance analysis of the experimental
digitalfreq
- 由于本人没有多少很好的源码,所以只能上传目前所做项目的相关参考文献资料。资料一的内容是数字分频器的参考文献,在fpga中数字分频器用的很多,文献对于设计小数分频器有一定的参考价值。-I am not much good as the source, we can only upload now doing projects related reference materials. Information content of a digital divider references in the
frequence_20
- 20分频器,具有一定的使用价值,自己可以试试看 。-20 frequence verilog code design and test
clkdiv
- 占空比可调 分频系数 都可随意设定的分频器,语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
fdivision
- 基于verilog的分频器,以及相应的test bench-A frequency divider based on verilog
Binarydivider
- 采用verilog编写的二进制分频器,常用于频率变化场合-Binary frequency divider using verilog prepared, commonly used in the frequency occasions
FPGA_fenpin
- 利用FPGA构建一个1:1的分频器,稍加修改即可改成频率可控获占空比可控的时钟输出。-Using FPGA to build a 1:1 divider, you can change the frequency slightly modified controllable duty cycle controlled by the clock output.
fenpin
- 分频器的实现将不同频段的声音信号区分开来,分别给于放大,然后送到相应频段的扬声器中再进行重放-FDCT Frequency Divider
divider
- 介绍了verilog设计中一种分频器的写法,很通用实惠,方便移植-Introduced the verilog design the wording of a kind of divider, a very common benefit, to facilitate migration
8fen
- 8分频器的VHDL源码,绝对正确,并且可根据本代码推导出各个2的幂数的分频器的编写原理。-FDCT Frequency Divider by VHDL .
eda_vhdl
- eda 学习板 电子色子源码 包括分频器解码器等部分-eda electronic dice source learning board
pulse1
- 分频器 等等大量代码 我测试过 可以-DDS2