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Lab9_adder4a
- 4位加法器的设计与实现.4位加法器框图，本实验中用Verilog语句来描述.nexy3.-With the implementation of.4 bit adder block design of 4 bit adder, the Verilog statement in this experiment to describe.Nexy3
adder4
- 基于VHDL的4位加法器。 由4个一位全加器级联构成。-VHDL-based 4-bit adder. One consists of four full adder cascade.
vhdl
- 通过VHDL语言，实现简单的多路选择器、串行加法器、并行加法器、计数器-By VHDL language, a simple multiple-choice, serial adder, parallel adder, counter
add
- Verilog 语言 加法器仿真调试过，没有任何问题 很简单的FPGA入门。-Verilog adder
adder_26
- 加法器 IPcore调用，如何添加调用，应该是26位的-Adder IPcore call, how to add call, it should be 26-bit
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
adder8
- 8位全加器，Verilog硬件语言源代码。最基础的加法器。-8-bit carry-ripple adder， the basic adder。Achieved by verilog source code.
adder8-carryripple-adder
- 8位加法器，最基础的加法器。硬件语言 Verilog源代码。-8-bit carry-ripple adder, The basic adder and the common one. Achieved by Verilog source code.
Desktop
- 8位流水灯模拟二进制加法器 keil C-8 water lights simulate a binary adder keil C
32bitvhdl
- 基于硬件描述语言的通过加法器实现的32位乘法器-Hardware descr iption language implemented by the adder 32 of the multiplier
flow_proc
- 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现 -In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation
32bit_add
- 32位进位选择加法器 用四位先行进位加法器扩展成32位二进制加法器-32 carry select adder Used four carry-lookahead adder extended to 32-bit binary adder
2.1.5P4-Adder-VHDL-and-Waveform
- p4_adder 奔腾4cpu的加法器,包括carry selectadder carry generator -p4_adder Pentium 4cpu adder includes carry selectadder carry generator
adder
- 加法器和累乘器，利用加法器和累乘器求所输入数的和与积。-Adder and multiplicative, using adder and multiplicative by the number of input and product.
Add_ahead
- 无流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator without pipelines
ImprovePipelineAdder
- 基于流水线加法器与寄存器结合在一起的相位累加器设计程序-vhdl implementation of phase accumulator with pipeline and registers.
jfqjava
- 一个java的加法器程序,这个程序并没有实现复杂的算法，仅仅是应用到了窗口的实现及运用。所以这个程序可以很好的学习了GUI知识-A Java adder program, this program does not realize the complex algorithm, is only applied to the implementation and application of the window.So this program can be very good to learn t
n_case
- 介绍了两个数字和数量B作为输入。向量是输出和它包含结果如果有特殊情况,否则未定义。最后,启动信号时看启用或禁用加法器块是否需要。 -Both number A and number B are introduced as inputs.Vector S is one of the outputs and it contains the result when there is a special case,otherwise undefined. Finally,enable signal
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.