搜索资源列表
jfq
- 加法器是实现两个二进制数相加运算的 基本单元电路。8 位加法器就是实现两个8 位 二进制相加,同时加上低位进位的运算电路。-Adder is to achieve the sum of two binary computing the basic unit of the circuit. 8-bit adder is to realize the sum of two 8-bit binary, at the same time together with the low binary
VDHL
- Verilog的135个经典设计实例,直流电机控制,游戏机,三态总线,加法器,锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
add
- Verilog hdl语言 常用加法器设计,可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
16bitCLA
- 基于Verilog HDL的16位超前进位加法器 分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
lab2-2
- 4位二进制加法器,vhdl实现,外带译码器部分,清晰简洁,可读性好-4-bit binary adder, vhdl achieved decoder part of the bargain, clear and concise, readable good
44
- 加法器测试平台,具有键盘输入,屏幕显示功能-Adder test platform with a keyboard input, screen display
testZ
- 八位加法器的原理图实现方法和一位半加器 全加器的原理图实现-Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of
myadd32
- 32位全程加法器,可以进行移位操作及多位多输入多输出加减法-32-bit full adder, shift operations can be carried out and a number of multiple-input multiple-output addition and subtraction
FPGA
- 基于FPGA数字乘法器的设计:数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一,本文设计了三种基于FPGA 的数字乘法器.分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
daima
- 用VHDL语言设计一个8位加法器: 在八位加法器代码一中:加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路,其中U1用来装载8位加法器中两个加数的低4位,而U2则用来装载高4位。在设计4位加法器时,定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB,将加数A和0并置后赋给AA,加数B和0并置后赋给BB,形成5位二进制数,这是为在做加法时发生溢出所做的处理,然后将加数AA与BB以及进位Cin相加赋给SINT,并将SINT的低4位赋给加数和S输
adder
- 本设计是做了一个32位超前进位加法器,能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件,可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
add32
- 32位加法器,verilog实现,且有仿真图像-32-bit adder and programed by veilog
add
- verilog实现的完整的加法器,包括测试文件等(Verilog implements a complete adder, including test files)
adder
- 实现四位加法器,适合初学者学习VHDL语言(it's an addler of four bits which is designed for the new designer of VHDL)
add.tb
- 加法器tb文件,用与对加法器进行仿真处理,通过modusim运行,适合新手参考。(add tb file and with the adder simulation processing, through the modusim run, suitable for novice reference.)
cnt_10
- 十以内的加法器,实现十以内的加法功能,最高位清零(en less than adder, to achieve the addition function within ten, the highest clear)
pipeline_adder
- 用于快速计算32位加法,共分5级锁存器,4个8位加法器(pipeline_adder it helps you to add 32 bits swiftly if you need more information,may call me by the website account,it's really helpful)
基于FPGA的四位加法器
- 基于FPGA的四位加法器verilog语言代码(be basaed upon FPGA adder4)
add_1p
- 用于FPGA的加法器实现程序,采用Verilog语言编写(Adder implementation program for FPGA)