搜索资源列表
PLUS
- 用VS2010中的MFC 编写的一个加法器小程序。- a plus machine.
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
adder
- 四位二进制串行加法器 VHDL语言 EPM240 数字逻辑实验-Four serial binary adder VHDL language EPM240 digital logic test
test8
- xilinx工程文件，test8.v是源代码，实现了逐位进位的加法器、减法器，和逻辑运算功能。运行通过，仿真成功。-Xilinx engineering documents, test8. V is the source code, to achieve the cascaded carry adder, subtracter, and logical operations function. Running through, the simulation is successful.
Sum
- 实现加法器功能的简单verilog代码，可以为初学者提供学习。-Achieve a simple verilog adder function code can provide learning for the beginners.
LAB3_1
- 一个八位加法器，利用四个全加器组成，并兼有溢出提示功能-An eight adder using four full adder composed, and both spill prompts
adder4
- 利用硬件语言FPGA Verilog语言实现4位加法器的运算-Using FPGA hardware language Verilog language implementation and operation of four adder
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
Adder
- 加法程序，是3个数字的加法器，很不错，我们可以用来做小游戏-Addition the program is three-digit adder, very good, we can use to make game
adder
- 一个初学者容易明白的加法器,大家可通过这个学到很多基础知识-a adder easy
count_60
- BCD码60进制加法器。。。。 编译通过，仿真通过-Compile, through simulation
JAVA
- 这个文件夹里是经典的Java源代码，其中包括类加法器，记事本等。-adder.java, notepad.java and so on
test
- 初学者小实验加法器，如果有熟悉java的联系哟-the Java fresh man can use to exercise themselves，i like to have a discussion with someone who like java
Java-code
- 这是一些经典的Java源代码，如加法器，小记事本，绘图板等，对初学者有很好的帮助-This is some of the classic Java source code, such as adders, small notepad, graphics tablet, etc., with a good help for beginners
add_10
- FPGA中基于Verilog语言的10位加法器设计，适合初学者学习FPGA-FPGA Verilog language-based 10-bit adder design, suitable for beginners to learn FPGA
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
adder4bit
- VHDL设计的四位加法器器，仿真测试正确，可以使用。-VHDL design of four adders, a simulation test correctly, you can use
f_adder
- 利用VHDL的语言，实现考虑进位的全加器，该程序带中的加法器带有使能端，可以更好地实现所需功能。-Using VHDL language to achieve considering the carry bit full adder, the program with the adder with Enable, can better achieve the desired function.
ISEadder
- 利用Verilog语言，基于ISE，设计加法器-ISE adder
summator
- fpga verilog入门经典系列完整版，下载即用:求和加法器-fpga verilog