搜索资源列表
adc
- 使用verilog 硬件描述语言编写的ad采样模块,希望对大家有用。(Using Verilog hardware descr iption language written in AD sampling module, I hope useful for everyone)
ece385sp16_lab4_adders
- 加法器, 三种加法器的实现。不同的逻辑速度和逻辑结构(adders, three types of them)
Half-Adder
- xilinx ISE平台提供1位半加法器,模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
设计实验二
- 在protues里可以直接运行,大神编写(In Protues can run directly, great God write)
verilog四则运算器
- verilog四则运算,包括加法器、乘法器、除法器,不过都是拾人牙慧,整理一下,供新手参考。(Verilog four operations, including the adder, multiplier and divider, but are written, tidy, for novice reference.)
poly
- 第一次作业 Java实现一个多项式加法器 写的不好,可以借鉴不要抄(First assignment Java implements a polynomial adder Writing is not good, can learn not to copy)
gray_counter
- 格雷码计数器实质包含了三个部分 格雷码转二进制、加法器、二进制转格雷码。通过quartus II 自带的Modlesim仿真验证了 能够实现二进制和格雷码之间的转换(Gray counter essence contains three parts, gray code to binary adder, binary gray code conversion. Modlesim simulation by quartus with II verified to achieve the conve
WPF_Validation_src
- 该项目是在WPF MVVM项目验证。各种选项进行一个简单的WPF应用程序建立两个数相加在一起。加法器的应用是作为一个包含两个文本框用于输入和计算按钮用户控件的实现。(The project is about validation in WPF MVVM projects. The various options are explored and a simple WPF application is built that adds two numbers together. The Adder
adder
- 此电路是一个基于Quartus II 的加法器,由两个半加器组成。(The circuit is an adder based on Quartus II, consisting of two adder.)
4472546
- 时钟信号输入端,要求编制一个顶层文件,产生具有自动加一功能的地址加法器()
DDS
- DDS直接数字合成器,里面包含相关的顶层文件,加法器,D触发器,mif文件(DDS direct digital synthesizer, which contains related top layer files, adder, D trigger, MIF file)
verilog add4
- 分两部分,基于verilog的四位和八位加法器设计,用synopsys的VCS仿真工具进行功能仿真,掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
add.v
- 这是verilog的加法器。它可用于超大规模集成电路设计。(This is an adder by Verilog. It can be used for VLSI design.)
try
- 利用xilinx公司开发的vivado平台中的IP核-加法器,实现加法(The addition of IP core adder to the vivado platform developed by Xilinx is applied.)
standarpkignal
- 时钟信号输入端,要求编制一个顶层文件,产生具有自动加一功能的地址加法器()
实验2
- 在Quartus II环境下,设计含有时钟同步使能的十进制加法器,并下载到实验板上进行验证。(Design a decimal adder with clock synchronization enable)
Com实验
- 实现一个简单的COM组件,实现一个加法器(Implementing simple Com components)
LAB
- SAM VHDL编码,包括数据选择器,加法器,简易逻辑电路,有限状态机等(FSM SAM ALU and many other different parts)
16qam
- 一个16QAM数字调制电路,包括时钟生成电路,m伪随机序列生成电路,串并转换电路,电平映射电路、载波信号发生电路、ASK幅度调制电路及加法器(A 16QAM digital modulation circuit, including clock generation circuit, m pseudo-random sequence generation circuit, serial parallel conversion circuit, level mapping circuit, car
8点fft
- 用quartus软件、verilog语言编写的8点fft源代码,代码简单易懂,整个代码只用了一个乘法器和一个加法器