搜索资源列表
microzed-axi-dma
- microzed (zynq) axi dma source vhdl
pg174-jtag-axi
- Good document for implement AXI jtag interface, helpfull for some one who wants to the design for FPGA
clk-axi-clkgen
- AXI clkgen driver for Linux v2.13.6.
axi-timer
- 这是Xilinx AXI定时器的说明手册，对于进行FPGA开发的工程师有参考价值 -The LogiCORE IP AXI Timer/Counter is a 32/ 64-bit timer module that interfaces to the AXI4-Lite interface.
axi-usb-2.0-device-demonstrating-performance-for-
- Xilinx KC705 axi usb interfacing
zc706-axi-dma-fifo-master
- zc706 axi-dma-fifo-master example
how-to-use-the-3-axi-configurations
- Used for AXI protocol firmware developments.
AXI-54
- this all about viviado AXI four light bus communication. it is good for every one who is intersted in studying vivado axi light interfacing-this is all about viviado AXI four light bus communication. it is good for every one who is intersted in study
axi_lite_user
- axi_lite_user官方样例，精简功能，适用于zynq系列axi总线(Axi_lite_user official sample, streamline function, apply to zynq series Axi bus)
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
AXI slave
- 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
slave
- xilinx Zynq 中的AXI总线 axi slaver模块(AXI bus Axi slaver module in Xilinx Zynq)
axi_dma
- 在zedboard开发板上采用vivado通过AXI进行DMA数据传输(Using vivado to transfer DMA data through AXI on zedboard development board)
AMBAaxi
- amba axi specification
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
axi-cdma
- xilinx7系列芯片cdma的使用，axi总线接口，包括SG模式(the cdma of xilinx zynq7)
my_led_ip
- 四通道axi LED灯控制器，用于嵌入式系统中的一些功能指示(The four channel Axi LED lamp controller is used for some function instructions in the embedded system)
AXI_testv1.00
- 添加ILA逻辑分析仪观测AXI总线时序，根据时序可以自行对AXI总线进行应用。(Adding ILA logic analyzer to observe the time sequence of AXI bus)
axi lite 接口
- 该文件完成了简单的axi lite 接口协议 Verilog 语言编程。欢迎交流讨论
emif2axi
- emif 接口转axi总线,测试功能正常使用，不包含仿真文件(EMIF interface to Axi bus, test function is in normal use, does not contain simulation files)