搜索资源列表
vgaverilog
- 本程序实现了基于FPGA/CPLD的VGA显示设计,简单易懂,可以输出8种颜色,即3位RGB颜色,共8种组合。连接FPGA的VGA口和液晶等显示器即可观察实验现象。-This procedure implemented based on FPGA/CPLD' s VGA display design, easy to understand, you can output 8 colors, the three RGB colors, a total of 8 combinations. FPGA
_11_vga_color_slip
- FPGA用Verilog编写VGA接口,可接在电脑显示器上-Written by Verilog FPGA VGA interface, which can be accessed on the computer monitor
DC
- 汉明码的解码电路,用VHDL实现,可以用于FPGA仿真-Hamming code decoding circuit, VHDL implementation, can be used for FPGA simulation
my_232
- 个人用verilog写的一个FPGA串口通信程序,程序测试成功,可以使用。-Individual by verilog written by one of the FPGA serial communication program that test, can use success.
pwm
- 这是用FPGA做的一个pwm波的程序,调试过的非常好用的程序,下载就可以用 ,占空比可以自己改-This is done with a pwm wave FPGA program, debug the program had a very easy to use, download you can use, the duty cycle can do it ourselves
SG_FPGA
- 2006年电子设计竞赛二等奖,多功能函数、信号发生器核心器件FPGA内部的原理图,主要模块用VHDL代码描述,包括PLL、相位累加器、波形算法和正弦波查找表,可实现0.005Hz~20MHz的多波形信号产生,频率步进值0.005,输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
caitiao
- 运用VHDL,Verilog语言编写的实现显示器显示彩条的硬件控制系统,下载到Virtex2Pro实验板FPGA上,外接显示器即可,相当于一个简单的显示卡驱动程序,不过是用纯硬件实现的-The use of VHDL, Verilog language to achieve color display of the hardware control system, downloaded to the FPGA board Virtex2Pro experiment, an external di
top
- FPGA实现dds,可调频,任意波形,键盘输入。三角正弦锯齿波都有-FPGA realizing, can change the frequency, any DDS waveform, the keyboard input. The triangle sine sawtooth wave
ep2c35_3.8_full_add
- 这个程序用verilog硬件语言编写。用来在FPGA内实现全加器。并且可以将输出显示在外部LED灯上等。-this program is writen by verilog HDL.it is the full adder for FPGA.users can read the result from the LEDs.
honglvdeng
- Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。他的设计描述可被不同的工具所支持,可用不同器件来实现。利用Verilog HDL语言自顶向下的设计方法设计交通灯控制系统,使其实现道路交通的正常运转,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过Xilinx ISE6.02和ModelSim5.6完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的交通灯控制系统中。-Verilog HDL as a standard hardware
DesignCPCIanalogonFPGA
- 本文实现了8通道的12位D/A模拟输出板卡的设计。该设计是基于FPGA的3U CPCI板卡,可以提供8通道的模拟电压和电流输出,各路电压输出范围可以配置成0~5V、0~10V、-5~5V或-10V~10V,各路输出电流可以配置成4~20mA、0~20mA或0~24mA。本设计摒弃了常规的CPCI接口芯片,采用FPGA十PCI IP CORE的设计方案,大幅度提高了系统的集成度和调试速度,缩短了系统的开发周期。方案使用专门的WDM (windows driver model)开发工具Driver
VHD
- 此为基于Xilinx的FPGA用VHDL实现的FIFO,已调通,可直接运行。-This is based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
uart_transceiver
- 一个通用串口通信FPGA程序。大家可以借鉴-a uart FPGA pragram.you can modify and use it in your project.
yibanjiafaqidesheji-EDA
- 基于FPGA的快速加法器的设计与实现,在VHDL环境中波形图显示出结果,可以用二进制,十进制,十六进制表示 -FPGA-based fast adder design and implementation in VHDL environment, the results in the waveform display, you can use binary, decimal, hexadecimal
my_adc1
- 020单片机ADC1采样程序;额外功能:main中主要实现与FPGA并口通信,总体实现FFT,不过FPGA部分没有上传,因此能实现的是ADC1采样。-020 SCM ADC1 sampling procedures additional features: main key to achieve in parallel with the FPGA communication, achieving an overall FFT, but the FPGA portion not uploaded
61EDA_B327
- 键盘鼠标的源代码(用FPGA实现,使用Verilog HDL编写,已经使用FPGA验正过了,完全可以用)-Keyboard and mouse the source code (using FPGA, written using Verilog HDL, has been a positive experience with FPGA, can be used)
e011_timingdesigner
- FPGA时序设计时必备的软件。可以有效的提高逻辑设计的速度,调整设计时的时序。-FPGA design timing necessary software. Logic design can effectively improve the speed of adjustment of the design timing.
rs232-demo-for-send-welcome
- 这个一个用于fpga上面的串口调试程序,基于vhdl语言编写,可实现welcome字符的现实功能。-Fpga above this one for the serial debugger, based on vhdl language, the reality can be realized characters welcome feature.
BasysDemo_ISEproject
- Digilent公司basys开发板的全套开发例程,代码,可用于仿真,下载。包括了基本的fpga外设单元。-Digilent development board' s basys complete development routines, the code can be used for simulation, download. Fpga peripherals, including the basic unit.
counter
- 本文介绍了基于FPGA的数字频率计的设计方法,设计采用硬件描述语言Verilog ,在软件开发平台ISE上完成,可以在较高速时钟频率(48MHz)下正常工作。该数字频率计采用测频的方法,能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t