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jiyu-FPGA-chaochengboxinhaochuli
- 了降低超声波流量检测过程中噪声对检测精度的影响，采用FPGA器件构建了FIR滤波器，并提出一种新颖的查表法替代滤波器中的乘法运算-In order to reduce the flow in the process of ultrasonic testing noise on the influence of the precision, based on FPGA device constructed the FIR filter, and put forward a novel queryi
fir-filter-in-Matlab-and-Modelsim
- 基于DSP Builder的fir滤波器，及在Modelsim上仿真工程文件，是在做基于FPGA的fir滤波器的一部分-The DSP Builder-based fir filter, and on the simulation project file in Modelsim is doing FPGA-based fir filter part of the
FPGA-using-for-SDR
- FPGA在软件无线电设计中的应用，AD、DA，FIR、CIC的设计-FPGA SDR
FPGA-FIR
- 基于FPGA的FIR滤波器设计方法的研究-Based on the FPGA FIR filter design method
designing-of-FIR-filer-based-on-FPGA
- 该文件是基于FPGA设计FIR滤波器设计的VHDL语言代码。-designing of FIR filer based on FPGA
FPGA-FIR
- FPGA实现 FIR数字滤波器方案研究！-FPGA implementation of FIR digital filter program.
FIR
- 基于FPGA的1000阶FIR数字滤波器-1000 order FIR digital filters based on FPGA
signal-fir
- FPGA实现FIR滤波器，对信号的滤波处理，其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
Filtro-FIR-en-FPGA
- Implementacion de Filtro fir en fpga
Filtro-FIR-sobre-fpga
- Filtro fir sobre fpga
THE-FIR-Base-on-FPGA
- 基于fpga的FIR滤波器实现，程序为11阶滤波器实现的源代码-Fpga-based FIR filter implementation, the source code
FPGA-FIR-filter-design
- 用数字逻辑语言设计一个十六阶的FIR滤波器，通过数字电路实现滤波处理-Digital logic language design a sixteen-stage FIR filter, the filtering process is implemented by a digital circuit
FDAtool-design-fir-filter
- 基于FDAtool及FPGA的FIR滤波器设计-FDAtool design fir filter
32-order-FIR-on-FPGA
- 基于FPGA的32阶FIR滤波器设计，研究了一种采用FPGA实现数字滤波器硬件电路方案；讨论了窗函数的选择、滤波器的结构以及系数量化问题-32 order FIR filter design based on FPGA, an FPGA implementation digital filter hardware circuit program discussed the choice of the window function, the structure of the filter co
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
fir
- 基于FPGA的低通滤波器的设计，仿真环境是QuartusII9.0。对信号进行低通滤波，编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
FIR
- 基于fpga的FIR滤波器设计,已通过modesim仿真结果正确,verilog编写-Fpga-based FIR filter design, has passed modesim simulation results are correct, verilog prepared
fir
- 该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用-design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language.
fir
- FIR滤波器的FPGA仿真与实现。欢迎分享，分享快乐。-The FPGA simulation and realization of the FIR filter.Welcome to share, share the happiness.