搜索资源列表
MSP430JIAdds
- MSP430和FPGA通信模块四个ROM,里面包含DDS程序代码,通信代码-MSP430 and FPGA communication module of four ROM, which contains the DDS code
top
- FPGA程序的top.v文件,主要实现DDS信号发生器功能,通过定时器,可简单实现输出幅值无极跳变-FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping
UseofFPGA
- 利用FPGA实现的DDS,可输出正弦波,输出频率可调-Use of FPGA implementation of the DDS, sine wave output, output frequency adjustable
FPGA_DDS
- 本文介绍了如何用VHDL进行DDS的设计,其中关键的相位累加器,正弦信号发生器等用VHDL描述-the DDS is depend on the fpga ,and we descr iption it use the vhdl
ad9851
- ad9851的中文资料,本人希望可以和喜爱DDS或者FPGA的朋友一起交流-Chinese ad9851 information, I would like to DDS and love of friends or the exchange of FPGA
DDSFPGA
- 基于FPGA的FFT功能实现,内有详细代码,并附有DDS的相关源码-FPGA-based FFT function realization, which detailed code, along with the related source code DDS
Study_on_Key_Technologies_of_n4-DQPSK_Modulation_a
- 本文首先研究可4一DQPsK调制解调系统中调制部分的基本原理和各个模块的设计方案,重点研究成形滤波器和直接数字频率合成器 (DireetoigitalFrequeneySynihesis,简称DDS),并针对各个关键模块算法进行matlab设计仿真,展示仿真结果。其次,研究调制解调系统解调部分的基本原理和各个模块的设计方案,重点研究差分解调,数字下变频和位同步算法,也针对其各个关键模块进行算法的Matlab设计仿真。然后用Matlab对整个系统进行理论仿真,得出结论。在此基础 上,采用超高速
DDS_Timing
- 数字频率合成器DDS,具有和单片机接口的直接数字频率合成器的FPGA实现代码(Verilog)-Digital Frequency Synthesizer
uatr_and_dds
- 实现通过PC来控制fpga发出波形,波的形状和频率可通过PC控制,波形利用dds来发出,这是当时我做的电子测量的课程设计。-Fpga implementation given by PC to control the waveform, wave shape and frequency can be controlled through the PC, waveform using dds to send, this is when I do the electronic measurement
dds_using_FPGA
- 用FPGA实现的DDS,简单实用,通过调试-Implemented with FPGA DDS, simple and practical, by commissioning
O_DDS_PHASE
- 包括了DDS设计的全部源码,其中相位和频率均可调,可直接应用于sopc/fpga设计中-DDS design includes all the source code, which can be adjusted for phase and frequency can be directly applied to sopc/fpga design
ISE_lab18
- 基于VHDL语言,通过调用Xlinx生产的FPGA开发板上的DDS核,产生正弦信号。并可进行仿真观察。-Based on VHDL language, by calling Xlinx FPGA development board produced by the nuclear DDS, sine signal. The simulation can be observed.
DDS_Adder
- DDS加法程序,用verilog程序写成,在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s
The-pulse-signal-generator
- 脉冲信号发生器:采用DDS技术实现脉冲信号的周期、脉冲宽度、幅值的数控调节。通过单片机与FPGA的并行通信技术将频率控制字及矩形脉冲数据传送给FPGA的双口RAM。模拟输出通道则将信号通过100MHz、8位D/A转换器将波形数据转换成模拟脉冲信号,最后通过高速运放构成的放大器放大,实现幅度连续可调。-The pulse signal generator: using the DDS technology to achieve the pulse signal cycles, pulse widt
wf1
- dds信号发生器,基于fpga的信号发生器,拥有基本的功能,是本人亲自编写,具有良好的稳定性和健壮性!我喜欢这个代码-dds signal generator, signal generator based on fpga, with basic functions,
DDS_single
- 基于FPGA的单路DDS函数发生器的实现 ,语言为Verilog-FPGA-based single-channel DDS function generator implementation language for Verilog
sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片,以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz,输出四路频率为70MHz的四相序正弦载波(相位分别为0°、90°、180°、270°)的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真,验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
DDS_sine
- DDS扫频信号源的FPGA实现,有的是verilog编写,欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
FPGAPDDS
- FPGA+DDS产生信号的设计方案,比较具体,希望对你们有所帮助!-FPGA+ DDS generated signal design, more specifically, you want to help!
No.4
- 使用C8051F005开发板,控制FPGA和高速DA来DDS,两路DDS输出,90或180或0相差-Using the C8051F005 development board, the control FPGA and high-speed DA to DDS, two DDS output, a difference of 90 or 180 or 0