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fpga1244131245d
- 基于FPGA的FIR数字滤波器的设计与实现。滤波器设计参数可实现17阶和32阶线性相位FIR滤波器-FPGA-based FIR digital filter design and implementation. Filter design parameters can be achieved on 17 order and 32 order linear phase FIR filter
program
- 1/100s计时器的FPGA实现，本设计的计时器能实现显示最长计时时间为1分59.99秒，且精度大于1/100s，计时器能显示1/100s的时间.-1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display
VerilogHDL_Emample
- 其他说明： 文中实例基本都不依赖实际具体的硬件，可以在任何厂家任何系列的FPGA/CPLD下综合使用（如Altera等，只要资源充足），还可以利用Synoposy公司的工艺库影射到ASIC，完全可以当作软IPCore使用。 -Other notes: the text does not rely on practical and concrete examples of basic hardware, manufacturers of any series in any of the
c51controlFPGA
- PWM控制直流电机FPGA驱动,可以使用按键控制，加速、减速、正转、反转、停止-FPGA-driven DC motor PWM control, you can use the button control, acceleration, deceleration, forward, reverse, stop
VHDL-based-taxi-meter
- 本源码介绍了一种出租车计价器的设计方案，并且是基于VHDL语言，可以轻松在FPGA/CPLD上实现-This source presents a taxi meter design, and is based on the VHDL language, you can easily in the FPGA/CPLD to realize
driverfromlcd
- 一个用FPGA控制12864液晶输出时钟信息代码，可以根据自己的需要更改。-A control with the FPGA code 12864 LCD output clock information can be changed according to their needs.
vga
- 通过FPGA器件控制RGB信号、行同步信号、场同步信号等信号，并参照有关标准，最后可以实现对VGA显示器的控制。-RGB signal through the control of FPGA devices, the line sync signal, vertical sync signals and other signals, and with reference to the relevant standard VGA monitor can be achieved on the fin
chuankou
- 串口，电脑可接受，可发送；fpga实验主板通过串口线同样可接收发送-Serial port, the computer is acceptable, can be sent fpga board experiments also can be received via the serial line to send
chengxu
- 基于FPGA的DDS信号发生器设计，可以运行并出结果-The spurious signal generator based on FPGA design，Can run and out the results
ourdev_461286
- 时钟分频器源代码，使用在fpga中，直接可以使用的源代码-Clock divider source code, used in the fpga, direct source code can be used
HD_7279_b
- hd7279在fpga控制下由按键控制数码管的程序，可以使得数码管循环显示，有闪烁功能-hd7279 under the control of the fpga digital control by the key control procedures, can make the digital control loop shows that flash function
signal-generator
- 基于FPGA的多功能信号发生器，可以更改频率，波形，占空比-FPGA-based multi-function signal generator, can change the frequency, waveform, duty cycle
FPQA-first-example-project
- 一个很好的FPGA的入门工程例子程序，可以方便初学乾很快掌握如果建立FPGA的工程和仿真-A good example of FPGA project entry procedures, dry quickly mastered beginner can easily create FPGA if the engineering and simulation
Day1
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
Day2
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
Day3
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
Day4
- 关于FPGA的文档，通过此文档可以更好的学习FPGA的运作和开发。-Documentation on the FPGA, through this document can better learn the operation and development of FPGA.
Clk_Div
- FPGA分频器的设计，通过修改参数值可以实现各种时钟频率信号。-Divider FPGA design can be achieved by modifying the parameter values of various clock frequency signal.
VGA
- 用于vga显示，和图像的旋转，本程序部分可用作VGA接口，在此基础上惊醒图形在FPGA中的存储，显示和旋转。-For vga display, and image rotation, this program can be used as part of the VGA interface and graphics on this basis, awakened in the FPGA, storage, display and rotate.
86verilog
- 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字 滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了 对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结 果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求- W ith t