搜索资源列表
FM_Transmitter
- This the MATLAB for the DSP working behind FM transmitters in FPGAs etc.-This is the MATLAB for the DSP working behind FM transmitters in FPGAs etc.
sha1-progect
- Xilinx XC2VP20 FPGAs. The complete SHA-1 chip Verilog source
usbconnchip-proj
- Xilinx XC2VP20 FPGAs USB interface sources - Xilinx XC2VP20 FPGAs USB interface sources
VGADISPLAY
- 这是一个在FPGA平台下对VGA显示的操作，已经在FPGA开发板上测试通过。-This is an example about VGA display in FPGAS platform,it is tested in the FPGA development board.
TVout
- TV Output for Xilinx FPGAs
VHDL-Lab1
- It is a good programming tech to design fpgas and ICs.
vga
- vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a
AdcInterfaces
- A VHDL Code for ADC Interfaces in FPGAs
xilinx_intc
- Interrupt controller driver for Xilinx Virtex FPGAs.
i2c_master
- This details an I2C master component for single master buses, written in VHDL for use in CPLDs and FPGAs. The component reads and writes to user logic over a parallel interface. It was designed using Quartus II, version 11.1. -This details an I2C mas
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
FPGA-design-and-verification-using-Simulink
- Xilinx System Generator for DSP is a MATLAB Simulink block set that facilitates system design. Targeting Xilinx FPGAs within the familiar MATLAB environment, System Generator for DSP gives you the ability to functionally simulate a design and use
Design-for-Embedded
- Design for Embedded Image Processing on FPGAs ，FPGA图像处理算法-Design for Embedded Image Processing on FPGAs
FPGAs_8051_kernel-develop
- FPGA用51内核开发代码及文件,一些简单的参考代码。-FPGAs develop code with 51 kernel and its files.
wp_wimax
- WiMAX, or the IEEE 802.16 standard for broadband wireless access, is increasingly gaining in popularity as a technology with significant market potential. This paper first provides an overview of the existing and developing 802.16 standards and t
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
filtro-vhdl
- Implementing Filters on FPGAs. This paper explains the process of designing a digital filter in VHDL.
lmk04800 family controller
- VHDL code to configure lmk04800 family pll chips, that is well tested in 7-series FPGAs.
tinycpufiles
- TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。 内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is
usbf_crc5
- 适用于刚入门FPGA 的人使用，简单的FPGA程序例程-Applies to people who are just touching FPGAs