搜索资源列表
DES_IP
- 是VDKL语言实现的DES算法，是一个IP核， 对于相关方面有很好的帮助-VDKL language of the DES algorithm is an IP core, related well with the help of
FPGA_common
- 关于FPGA的一些常识及含IP核的VHDL设计源代码。-on FPGA with some common sense and VHDL IP core design of the source code.
LPM_ff
- VHDL中IP核之参数化触发器中文使用介绍-VHDL IP parameters of the nuclear trigger on the use of Chinese
LPM_sub_add
- VHDL中IP核之参数化加减法器中文使用介绍-VHDL IP parameters of the nuclear modified instruments used on the use of Chinese
USB2.0IP_core_Verilog
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
DesignofTrainCommunicationAdapterBasedonSOPC
- 介绍了MVB总线帧结构，并完成了用于网络连接的MVB总线访问IP核的设计。-introduced the MVB bus frame structure, and completed the network connection for the MVB bus visit IP core design.
FFT_IP
- Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
altera+dpd
- 数字预失真在通信领域内IP核的开发文档，包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
mc8051_vhdl
- mcs51的vhdl IP核,是每个学习FPGA的必经之路，希望一起探讨-mcs51 the vhdl IP core, each is a must to learn FPGA, hoping to explore together
8051inVHDL
- 8051的VHDL IP核，很不错的东西-8051 VHDL IP core, a very good thing
~CDDBNY834200PDF
- 探讨RISC32处理器设计中三个关键问题包括多媒体指令集扩展设计、流水线微结构优化设计以及使RISC32成为一个真正IP核的其他相关设计问题-explore RISC32 processor design three key issues, including the expansion of multimedia instruction set design, pipelined micro-structural optimization design and make RISC32 beco
LCD_IP_code
- LCD的通用驱动电路IP核设计..... -generic LCD driver circuit IP Core Design ...
my_ip_core
- 在quartusII下用verilog语言自己写的IP核，对FPGA开发初学者有帮助的。-in quartusII verilog using their own language to write the IP core, FPGA development beginners to help.
led_pwm
- 用硬件描述语言实现的灯控IP核，可实现至少256种颜色的真彩变换。-using Hardware Descr iption Language lights control IP core can achieve at least 256 colors transform the sleekly.
fftipcore
- 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
fft
- VHDL语言编写的fft变换的ip核代码 对算法感兴趣的可以
pci_core
- PCI logicore,在某网站上下载的ip核文件，希望具有参考价值，
Audio_DAC_FIFO
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。
DM9000A
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻易实现对dm9000a网卡的控制。
VGAControllercomponent
- altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以轻松控制vga的显示，十分难得哦！