搜索资源列表
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
mc8051-IP
- VHDL 8051 IP, VHDL写的8051的IP核。-VHDL 8051 IP
AES-IP-core-key-expansion-module
- AES IP核密钥扩展模块设计与仿真（设计过程及程序，测试程序）-AES IP core key expansion module design and simulation (the design process and procedures, test procedures)
AES--IP-core-architecture-design
- AES算法分析及其IP核体系结构设计（包括设计过程及代码）-AES algorithm analysis and its IP core architecture design
AES-IP-core-encryption-module-design
- AES IP核加密模块的设计与仿真(包括设计过程及代码)- the AES IP core encryption module design and simulation
AES-IP-core-control-module-design
- AES IP核的控制模块的设计与仿真以及系统集成与仿真-AES IP core design and simulation of the control module and system integration and simulation
USB2.0-IP
- USB2.0 IP核源代码，经典好用！写这么多真没意思！-USB 2.0 IP core source code, easy to use classic! Write so really boring!
VERILOGUSB2.0-IP
- USB IP核 verilog 语言 完整的use ip核-use ip verilog HDL
IP-coreincluding-VHDL-and-Verilog
- 芯片设计必须解剖的IP核（包含VHDL和Verilog代码）-The IP core chip design must anatomy (including VHDL and Verilog code)
uart-IP-Core
- 串口的FPGA VHDL的IP核 可以直接调用使用-Serial FPGA VHDL IP core can be called directly use
8051-IP-Core
- 8051的IP核，可以使用FPGA IP节点导入此IP核，实现单片机的功能。-8051 IP core can be used the FPGA IP node to import this IP core microcontroller functions.
crc-ip-core-usage
- CRC 编译码IP核的使用方法，仿真图和matlab的结果对比对比，fpga编程时使用-CRC encoding and decoding IP core use simulation in Fig the Matlab results contrast contrast
viterbi-ip-core-using-mothed
- FPGA的Viterbi译码器IP 核的使用说明，简单方便，一目了然。还能进行tcm译码，功能强大呀-Instructions for use of the FPGA Viterbi decoder IP core, easy glance. Can tcm decoding powerful!
verilog-ip-core
- verilog ip核，源代码，ethernet， video_compression_systems-verilog ip core source code, ethernet, video_compression_systems
8051-IP-core
- 这个整体的代码是8051的IP核，相信对于学习处理器和CPU架构的朋友，都会有很大帮助。-The overall code 8051 IP core, I believe that learning processor and CPU architectures friends, there will be a great help.
ARM-Verilog-HDL-IP-CORE
- ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。-ARM processor IP core, written in verilog processor and CPU architecture knowledge.
IP(1)
- 全功能硬件扫描键盘控制器IP核的实现，属于比较前沿的的键盘扫描方法-The realization of the full-featured hardware scanning keyboard controller IP core, belonging to compare the forefront of keyboard scan
SPI-IP
- 比较经典实用的ip核，对初学者有很大的帮助，语言比较简单。-Classic and practical IP core, a great help for beginners, the language is relatively simple.
ARM-Verilog-HDL-IP-CORE
- ARM Verilog HDL IP CORE， ARM IP核，采用verilog编写-ARM Verilog HDL IP CORE, ARM IP core, using verilog write
Altera-SDRAM_controller-IP-CORE
- Altera的SDRAM IP核代码，支持源码创作-Altera s SDRAM IP core code to support the creation of source