搜索资源列表
8051
- alter公司的mcu核，8051ip核，为quartus2设计，其他应该兼容 -alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
SDRAM_ipcore_
- Altera SDRAM ip核详解-Altera SDRAM ip nuclear Detailed
lcd_tri_12864
- lcd模块128x64 ip核 Avalon三态总线-lcd128x64 Avalon tristate
FFT_verilog
- verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
ethernet
- 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
SPI
- 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
IP
- 1）8位和24位bmp文件的打开，保存，自动判别文件类型并进行相应的设置。 2）对同一副bmp图像的多视图显示，包括：一般图像视图，直方图视图(支持彩色)， 图像属性视图，24位bmp的RGB各分量视图。 3）各种卷积核的滤波操作。包括：拉普拉斯二阶微分算子，LoG算子， 高斯平滑算子，sobel垂直/水平边缘增强算子，sobel边缘强度算子，两种 不同半径的圆形滤波器，另外canny边缘检测算子也可以在程序中使用。 4）8位24位bmp图像之间的相互转化。 5
10100MIP
- 以太网10100M IP核Verilog源码(可综合)\以太网10-100M IP核Verilog源码，可综合-10100M IP Ethernet core Verilog source code (which can be integrated) \ 10-100M IP Ethernet core Verilog source code can be integrated
IP
- ALTERAL的stratix4的IP核的使用讲解PPT，便于理解Stratix的IP核调用-The IP core stratix4 ALTERAL the use to explain the PPT, to facilitate the understanding the Stratix of IP core call
q_sys
- PCIe ip核。使用Quartus II 11.0，在Altera开发板4cgx15上验证通过。-PCIe ip core. Using the Quartus II 11.0, in the Altera development board 4cgx15 verify through.
8051_ip_core
- 8051微控制器的ip 核的vhdl源代码,其中包含了相应的测试程序.-8051 micro-controller ip nuclear vhdl source code, which contains the corresponding test procedures.
IPOFPIC
- pic单片机的源代码,基于此IP核可以自己修改单片机的外围设备,并在此基础上开发自己的单片机.-SCM pic source code, based on this IP core can modify MCU peripherals, and on this basis to develop their own single-chip microcomputer.
I2C
- 详细描述了I2C的技术规范 版本号为2.1 是采用VHDL编写I2C的IP核的一本不错的参考资料-A detailed descr iption of the I2C specification version 2.1 is the use of VHDL for the preparation of the IP core I2C a good reference
vhdl_source
- MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA