搜索资源列表
KEIL-PLL-wizard-2
- KEIL PLL WIZARD_Calculator FOR PLL Cofficients
Deltaementation
- Delta_Sigma调制 锁相频率合成器的设计与实现-Delta_Sigma modulation PLL Frequency Synthesizer Design and Implementation
PLL
- matlab-simulink的锁相环模型-pll model
pll
- quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
10.1.1.19.9992
- complete project design for pll and dds
8616039-PLL-Design-Part-2
- Phase-Locked Loops for High-Frequency Receivers and Transmitters–Part 2 by Mike Curtin and Paul O’Brien The first part of this series of articles introduced the basic concepts of phase-locked loops (PLLs). The PLL architecture and princip
38504873-pll
- Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
An-example-program-for-PLL
- What I found on Internet, it s a matlab program for phase-locked loop
PLL-and-Frequency-Syn
- 老外的一本绝版好书，有钱买不到的东西哦，收藏起来吧-Foreigners an out of print books, there are things money can not buy Oh, collectors get up
PLL-Dynamic-Reconfiguration
- 介绍了Spartan系列FPGA的PLL动态配置，很有参考价值-Introduced the Spartan series of FPGA' s PLL dynamic configuration, a good reference
avr--pll
- avr 单片机控制C450 后板PLL锁相环程序-PLL control C450 avr program after the board
SW-FM-Receiver-Controller
- 短波调频接收机控制系统，基于PIC16F877A 被控制芯片为MC145155-2锁相环。 采用一个LCD1602显示整机工作状态。 包含单片机部分的Proteus仿真.-SW-FM Receiver Controller based on PIC16F877A MCU to control MC145155-2 PLL. I use LCD1602 to display working status. include Proteus simulation .dsn
PLL
- this code is for activating the pll unit of lpc2148( arm7). in this way you can exceed your crystal clock. this code is by keil uvision compiler and works on lpc2148 from nxp.co enjoy it
pll
- 运用MegaWizard工具直接生成PLL模块，并用modelsim进行仿真。-failed to translate
verilog
- 数字锁相环电路verilog源代码 开发环境quartus-Digital PLL circuit verilog source code
DPLL
- 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
a-new-digital-PLL
- 基于FPGA实现的一种新型数字锁相环设计。该设计是用VHDL来实现的，个人觉得不错，所以传上来和大家分享-FPGA-based implementation of a new digital PLL design. The design is to use VHDL to implement the individual feels good, so come and share transfer
pll
- The ltering operation of the error voltage (coming out from the Phase Detec- tor) is performed by the loop lter. The output of PD consists of a dc component superimposed with an ac component. The ac part is undesired as an input to the VCO, h
softwarephaselockedloop
- 在电网电压频率波动或者三相不平衡的情况下,硬件锁相很难准确检测到基波正序的相位。在结合PWM整流器空间矢量解耦控制算法的基础上,将软件锁相环技术应用在PWM整流器控制系统中,并用仿真和实验验证了该方案的可行性。实验结果表明,该方案解决了电网电压频率波动及三相不平衡时的相位同步等问题,并在工程上具有一定参考价值。-Frequency or voltage fluctuations in three-phase unbalanced case, the hardware lock is diffic
code
- PLL中的TDC和DCO代码,是TI公司团队的，相当经典的代码，非常不错-the code of TDC and DCO