搜索资源列表
MB1504
- 锁相环芯片mb1504的烧写程序，能预置前置分频数和分频比！-PLL chip mb1504' s Shaoxie program can pre-pre-sub-sub-frequency and frequency ratio!
255
- 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
pic877a_LMX_2326true
- pic16f877a 的全功能程序,带A/D转换,串口通信,PLL控制LMX2326,用于1G 频谱仪 的全部程序,超值.-pic16f877a 1g SA program all.
PLL(lin)
- 一个用MATLAB 实现的锁相环路得程序-a program of phase loop link using the tool of simulink
pll
- 该程序用matlab实现求两直线的交点，显示直线和交点坐标。-Present two lines intersection
altpllpll
- 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
PllLogicModel
- 用Verilog语言编写锁相环（PLL）的经典文章，很实用！-Verilog language with phase-locked loop (PLL) classic article, very practical!
PLL_Configuration
- Simple Program to configure PLL in LPC2148-Simple Program to configure PLL in LPC2148
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
ppl
- 锁相电路是相位锁定环(Phase Locked Loop)的简称，主要由鉴相器、环路滤波、压控振荡器成 。主要是要掌握LabVIEW图形化编程特点，-PLL circuit is phase-locked loop (Phase Locked Loop) for short, mainly by the phase detector, loop filter, VCO into. Mainly to grasp the features of LabVIEW graphical programm
111pll
- 锁相环PLL原理与应用入门教程，很经典，值得一看-Principle and Application of phase-locked loop PLL Tutorial, very classic, worth a visit
pll
- HSPICE锁相环电路，为HSPICE提供的demo程序。-HSPICE PLL circuit for HSPICE to provide the demo program.
time_model_PLL
- PLL的simulink仿真模型，希望能有用，谢谢大家-PLL in simulink simulation models, hoping to be useful, thank you
pll
- freescale单片机PLL功能的应用，实现小灯的闪烁-freescale MCU PLL enabled applications, flashes of small lights
pll
- 基于DSP BF-535实验板,实现通过四个按钮改变系统时钟的功能-Experiment based on DSP BF-535 board, to achieve the four buttons to change the system clock through the function
analogModulation
- analogique simulation matlab de p-analogique simulation matlab de pll
PLL
- 一个基于FPGA的设计，使用锁相环，可以输出多个不同频率的时钟-failed to translate
PLL_example
- Sample PLL 3rd order Code
pll
- 锁相环的常见问题解答，对于全面理解，和研究锁相环的各种指标，有非常好的指导作用-PLL FAQ for a comprehensive understanding of, and the various indicators of phase-locked loop, a very good guide