搜索资源列表
pll
- fpga中pll时钟实现的源代码，可实现倍频或分频
A.spur-free.fractional-N.pll
- A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it i
pll.m
- pll 的一段吗狄梵思黛发的发射点法 的发射点法
Matlab-pll
- 附件里的代码，里面有详细过程说明： Phasell.m pll.m
PLL
- 关于在FPGA或CPLD锁相环PLL原理与应用,介绍用FPGA的分频技术.
PLL
- pll算法是来自经典的DSP的C程序和汇编程序库
PLL
- PLL 时钟模块 Quartus II平台的简单设计实例 附仿真波形
PLL
- 国外一篇很好的数字锁相环（PLL）设计文档（解压后PLL.pdf），不可不看呦！
pll
- 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
A New Phase-Locked Loop (PLL) System
- An enhanced phase-locked loop (PLL) system is presented and its properties and performance characteristics are investigated. Advantages of the proposed PLL structure over the conventional PLLs including its capability of direct estimation of ampli
用于仿真PLL环路增益噪声的例程
- 程序模拟了pll中PFD,VCO,CP,LOOP-FILTER等各部分的噪声性能，并进行整个链路的仿真优化，仅供参考。
数字PLL
- verilog写的数字PLL
verilog全数字锁相环pll
- verilog全数字锁相环，用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
lattice的PLL调用
- lattice的PLL模块实现，以及verilog的实现
PLL.该程序是基于c8051f120单片机开发
- 该程序是基于c8051f120单片机开发的、关于使用其内部锁相环为系统时钟。比较适合于初学者,The program is based on c8051f120 MCU developed on the use of its internal PLL for system clock. More suitable for beginners
pllverilog 完成pll锁相环的设计
- 基于FPGA的程序编写，完成pll锁相环的设计，实验证明次程序是完整的-FPGA-based programming, complete pll PLL design, experiments show that second program is complete
PLL_IN_MATLAB.rar
- PLL in Matlab for FM Demodulation,PLL in Matlab for FM Demodulation
PLL_grt_rtw.rar
- C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型,C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
PhaseNoise.rar
- 小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声, 传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功 能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的 发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相噪性能。,Fractional-N technology to s
suoxianghuan.rar
- 锁相环（PLL）simulink仿真，加深对PLL的理解,Phase-locked loop (PLL) simulink simulation, to deepen understanding of the PLL