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Ams_7b_8a_8b
- PLL simulation in simulink
593352pll
- 使用VHDL编写的数字PLL，对于想在FPGAzhong灵活使用时钟 的人有帮助。-Prepared by the use of VHDL digital PLL, the FPGAzhong would like flexibility in the use of the clock to help the people.
Mod-Demod-FM
- it is and Modulator and Demolator on FM, it helps you to build it with a VCO and a PLL LM565
ADF4360-7(350-1800)
- 介绍了ADF4360-8芯片的功能、内部结构、引脚排列及典型的应用电路及其评估板。ADF4360-8是集成的整数N合成器和压控振荡器（VCO）。芯片内嵌一个基准输入部分、N计数器和R计数器、相位频率检波器（PFD）和充电泵、多路复用器和锁定检波器、输入移位寄存器、控制锁存器、N计数锁存器、R计数锁存器。它可用于产生系统时钟，作为测试设备，用于无线局域网（LAN），作为闭路电视（CATV）设备。ADF4360-8EB1评估板可以让用户评估ADF4360-8频率合成器PLL的性能。 -Intro
pll_tools
- pll programs for 2nd , 3rd 4th order
PLL
- Programs for the book of Phase Locked Loop :design simulation and applications-Programs for the design of Phase Locked Loop circuits
matlab1
- 61549798pll_matlab[1]课程设计做的PLL,里面有关线性和非线性的都有,大家可以-61549798pll_matlab [1] course design done PLL, on the inside of both linear and nonlinear, we can
Springer.CMOS.PLL.Synthesizers.Analysis.and.Design
- Springer出版的非常好的CMOS PLL (锁相环设计)方面的资料.-Springer.CMOS.PLL.Synthesizers.Analysis.and.Design.Nov.2004.eBook-LinG
PLL
- PPL讲义，关于鉴相器方面的技术资料，对于用单片机编程有好处。-PPL notes, phase detector on the technical information, good use of single-chip programming.
slla120
- 锁相环是一种反馈电路，其作用是使得电路上的时钟和某一外部时钟的相位同步。PLL通过比较外部信号的相位和由压控晶振（VCXO）的相位来实现同步的，在比较的过程中，锁相环电路会不断根据外部信号的相位来调整本地晶振的时钟相位，直到两个信号的相位同步。-PLL is a feedback circuit, and its role is to make the clock circuit and a phase of external clock synchronization. PLL signal
simple_PLL
- This m_file uses a PLL to demodulate an FM modulated carrier
PhaseLockedLoop
- This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both
PLL
- 用VHDL和matlab编写的数字锁相环电路。-Matlab with VHDL and digital phase-locked loop circuit prepared.
adsx
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
pll_acsidefilter
- PLL AT AC SIDE FILTER
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
dds9851
- 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct
simple_pll_3
- pll mode for matlab simulation
TSA5059_PLL
- TSA5059 PLL PIC Test OK