搜索资源列表
AMBA-Bus_Verilog_Model
- 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_R
true_dual_port_ram_dual_clock
- 双端口ram的verilog程序，经过验证，可编译可用,-dual pot ram
VHDL语言实现的arm内核
- 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码，以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
ram_verilog
- 本程序用verilog实现实现了RAM读写功能-This programe describe the properties of reading and writing ram.
InvMod_test
- verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
DW8051_ALL
- 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is desi
fifo_test
- FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
in_out_put
- 双向RAM的Verilog程序，能实现双向传数据-The Verilog bidirectional RAM process, to achieve a two-way mass data
61EDA_H182
- ram模块的Verilog程序的实现，还有好多的字要打-ram modules, Verilog program implementation, there are a lot of words Yaoda
ramtest
- 用verilog语言往内部FPGA的sram中读写数据，即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram
DualPortRAM
- 此程序是Verilog HDL语言读写RAM的程序希望大家有用-This is Verilog HDL Promang
dp_ram
- 双口RAM的设计，采用Verilog HDL语言编写。-Dual-port RAM design, using Verilog HDL language.
idt71v416s10
- code for ram in verilog hdl
SOU
- 这是用C写的正弦函数定点数据生成代码，内容是生成verilog中RAM或者ROM和Matlab处理时的所用的数据。-It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
ex9_cof_M4K_test1
- ram的Verilog实现，很不错-ram of the Verilog implementation, very good ~~~~~
fh_ram_s_w_r_16_512
- 单口串行可读写16x512的ram的verilog源代码-singal serial writeable and readable 16x512 ram
Abus_fifo_ram_V1
- 该模块是基于verilog语言编写的双口ram模块，可将该该模块作为缓存模块使用-surpost ram write/read
AWSEQ_RAM_RW_A_DFF
- Verilog AWSEQ RAM DFF Verilog code