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colorchange
- 用verilog hdl实现色彩空间转换,rgb到ycbcr-with Verilog HDL achieve color space conversion, rgb to RS
YCbCr_to_rgb
- 颜色空间转换代码,ycbcr对rgb的转换verilog代码.YCBCR的格式是ITU601格式.-color space conversion code, RS right rgb conversion Verilog code. YCBCR format is ITU601 format.
encode
- Quartus下的RS(5,3)编码器的源程序,用Verilog语言编写。
RSverilog
- RS编码的verilog源代码,拿来和大家分享
RS232
- FPGA实现RS-232串口收发的Verilog程序,已经调通。
RSencode
- 包含RS(10,8)的verilog源程序,加法器的verilog源程序,卷积码的verilog源程序
mimasuo
- vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验
RS485EN
- RS485的双向通信处,正在为此头疼的同学们可要注意了,这个可以解决你们双向通信过程中的很多问题哦-Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
RS_5_3_CODEC
- 完成RS(5,3)编码程序,运用Verilog语言。-Complete the RS (5,3) coding process, the use of Verilog language.
RS-232
- 串口通信模块Verilog代码及相关文档-Serial communication module Verilog code and related documentation
RS-232
- verilog实现RS-232串口通信,经过功能仿真,完全能够行得通。-realise RS-232 by using verilog HDL
mulitcpu
- 用verilog HDL语言或者VHDL语言来编写,实现多时钟周期CPU的设计。能够完成以下二十二条指定(均不考虑虚拟地址和Cache,并且默认为小端方式): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs,
rs
- RS(255,239)verilog代码,已通过quartusII仿真,满足设计要求,需要的可以拿去参考-RS (255,239) Verilog code, through quartusII Simulation meet the design requirements, the need to take reference
RS-232CUART
- 主要是利用FPGA进行串口的通信 其中利用到FPGA的开发软件QUARTUS -verilog NIOS UART
verilog-uart
- UART(Universal Asynchronous Receiver Transmitter,通用异步收发器)是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路,分析UART的传输时序并利用Verilog HDL语言进行建模与仿真,最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receive
RS
- 通过verilog hdl语言实现RS编码器与译码器的设计-Verilog hdl language through the RS encoder and decoder design
RS-422standardmodulev2
- rs422标准通讯模块 异步收发 verilog语言编写-rs422 standard communication module asynchronous receiver verilog language
1---Serial-interface-(RS-232)
- Verilog HDL编写的RS232通信接口,包含RS232接口通信原理解析和编程实现文档-Verilog HDL prepared by the RS232 communication interface, including RS232 interface communication principles of parsing and programming documents
RS(204-188)decoder_verilog
- 采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}-Verilog achieved using the finite field GF (28) weak dual basis multiplier
rs_200_168
- Verilog实现的DVB(200,168)的RS编解码程序,xilinx 平台,经过验证(Verilog implementation of DVB (200168) RS codec program, Xilinx platform, verified)