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EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
program.rar
- MIMO-OFDM技术，以及算法仿真程序，空时编码，V-BLAST编码算法等。,MIMO-OFDM technology, and simulation algorithm, space-time coding, V-BLAST encoding algorithm.
license
- FreeScale CodeWarrior for PowerPC V 8.8 License
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
jsTree.v.0.9.6
- ssh+jquery生成树-java+jquery+ssh。。。。。。。。。。。。。
C-V
- C-V模型实现灰度图像和彩色图像的分割,运用水平集方法实现曲线演化-using Chan-Vese model color image segmentation
dswfsdk-2.4.2
- swf sdk v 2.4.2 for delphi 7
AT070TN83V11
- 群创7寸AT070TN83 V.1 液晶屏PDF详细资料-AT070TN83 V.1
jsTree.v.0.9.8
- 一个很强大的jsTree 插件， 带演示，演示，源码
V-f_2
- A New Induction Motor V/f Control Method Capable of High-Performance Regulation at Low Speeds
SiRFatlasV-Datasheet
- CSR/Sirf Atlas V, GPS/PND方案, ARM1136+DSP双核处理器-CSR/Sirf Atlas V, for GPS/PND, ARM1136 with GPS Baseband processor
UNIX_SysV_R4.2.tar
- USL UNIX System V Release 4.2 Version 1 source code for i386
fangzhen
- matlab 代码,实现了ITU-T V.32建议的 modem 整体仿真实现。-matlab code, implementation of the ITU-T V.32 proposed modem achieve the overall simulation.
siphon-v.666.tar
- 使用嗅探器侦听操作系统类型的程序- Uses the sniffer to intercept the operating system type the procedure
Delphi_HTML Components v 8 2 pro Source Code
- Delphi_HTML Components v 8 2 pro Source Code
lighttpd-1.5.0.r2294.modcache.v.1.6.1.tar
- 带mod_cache的lighttpd服务器,性能有很大提高,可以让一个1G带宽跑满不是神话 使用是直接解压后./configure -C就可以生成mod_cache模块的lighttpd.-The lighttpd server with mod_cache, performance has greatly improved, allowing one run over 1G bandwidth is not a myth after use is a direct unzip./Con
V++bookmart
- V++技术内幕-读书笔记.doc-V++ Technology Insider- Reading Notes. Doc
C-V
- 本程序采用半隐式方案实现变分水平集图像分割方法中的“C-V”模型(Active contour without edge)-This procedure used the program to achieve semi-implicit variational level set image segmentation methods in the
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
VBLAST
- 一套完整的V-BLAST系统，包括发射端的多种调制以及多种接受算法，信道为瑞利信道。-A complete set of V-BLAST system, including a variety of modulation transmitter and a variety of acceptable algorithm, channel for the Rayleigh channel.