搜索资源列表
ads7822
- 利用Verilog语言实现读取ADS7822模数转换芯片的串行输出数据-it is convinient for us to use A/D converter to get digital data
aes
- verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
18a
- 匹配滤波器设计，VERILOG实现的，比较好的哦-Matched filter design, VERILOG implementation, and better oh
robertvision
- 基于FPGA的嵌入式机器人视觉识别系统模块源代码，也包括了所有硬件设计资料，是VERILOG格式-Embedded FPGA-based Robot Vision Recognition System module source code, including all hardware design information
DDR3
- DDR3控制器，基于Altera平台，修改管教后直接可以下载进PFGA-DDR3 controller, based on Altera platform, modify the discipline can be downloaded directly into the PFGA
rs232
- 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
uart
- 串口通讯 PC发送FPGA接受后回传 verilog语言-uart verilog
FPGA_examples
- FPGA工程例子.verilog HDL语言编写；-FPGA project examples. Verilog HDL language
mult_piped_8x8
- 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
LMS_filter
- verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
UART
- 本人自己编写的FPGA异步串口通信模块（UART），基于QuartusII环境，verilog语言编写，包含仿真和全部程序及说明，验证通过，具有很好的稳定性和参考价值！-I have written of the FPGA asynchronous serial communication module (UART), based on QuartusII the environment, verilog language, including simulation and all the pr
FSK
- 频移键控FSK的Verilog实现，带测试文件，并在FPGA开发板上成功验证-Frequency Shift Keying FSK the Verilog implementation, with the test file, and successfully verified in FPGA development board
OV7620_TEST
- FPGA驱动OV7620程序代码，SCCB部分由单片机完成，FPGA负责完成图像处理和TFT液晶的显示。经试验，效果不错！-FPGA-driven OV7620 code, SCCB completed in part by the microcontroller, FPGA responsible for the completion of image processing and TFT LCD display. The test, good results!
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
1
- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
FPGA_PWM
- 用Verilog语言编写的FPGA控制PWM的程序.利用码盘脉冲进行调速,进行过简单试验,可用.没有经过长期验证.做简单修改即可应用!-Using Verilog languages FPGA control PWM procedures. Using pulse code disk for governor, conducted a simple test that can be used. Not after a long-term verification. To do a simple
vga_control
- vga 控制器的verilog 源码 ，fpga上可实现图片的显示-vga controller Verilog source code, fpga achievable picture display
TS201_LINK_TRANSFER
- Ts201 link port verilog