搜索资源列表
URAT_VHDL
- URAT VHDL程序与仿真 各程序运行环境为MAXPLUS_-UART procedures and VHDL simulation environment for the operation of the procedures for MAXPLUS_
puerto-Uart-rs232
- UART PORT VHDL USING DE2-115
uart
- VHDL语言模拟异步串口程序,实测可用,欢迎下载-uart source design by FPGA
UART
- UART (serial) protocol in VHDL with receive & send
fpga-KEY-UART-SRAM
- fpga KEY UART SRAM 驱动 程序 VHDL VERILOG-fpga KEY UART SRAM driver VHDL VERILOG
uart
- uart_reciver with vhdl (ISE Design Suite 14.7)
uart
- VHDL串口程序 波特率115200 功能:返回所发一字节数据的各位取反-UART BAUD 115200
kehshechenxu
- 编制一全双工UART电路,通过试验箱MAX202E转换成RS232电平,与计算机进行通讯实验,设置8个按键,按键值为ASIC码“1”~“8”,通过串口发送给计算机,在计算机上显示键值,同时在数码管最高位显示;计算机可发送“0”~“F”的ASIC码,FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。 要求:波特率为三种 1200、2400、9600,由1个按键选择,3个LED分别指示; 数据格式为1位起始位、8位数据位和一位停止位; 上位计算机发送接收软件可使用
UART_FPGA
- 使用VHDL写的UART收发模块,测试功能正常(Using VHDL to write the UART transceiver module)
用FPGA实现UART
- 用fpga实现异步串行通信。通过串口助手接收与发送(Implementation of serial communication with FPGA)
test42_CoreABC
- VHDL How to use CoreABC-IP with uart microsemi project
uart_latest.tar
- UART的VHDL建模代码,是一个标准的IP核(UART's VHDL modeling code is a standard IP core)
UAET_323_to_flow_led
- VHDL 实现串口收发并点亮流水灯,仿真成功(VHDL realizes serial port transceiver and lighting water lamp)
uart_working_transmit
- UART transmission vhdl code, for nexys 3 fpga board
uart_receiver
- Uart receiver VHDL code
uart_design
- UART设计的VERILOG代码,具有FIFO功能,能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
5_uart_test
- 基于xilinx的Artix7实现UART通信(UART communication based on Xilinx Artix7)
uart
- RS232通信程序,用于实现PC端与FPGA之间实现串口通信(RS232 communication program for realizing serial port communication between PC and FPGA)
vhdl的串口UART编写
- 该资料是用vhdl语言实现串口UART的编写,程序包括发送模块,接收模块,波特率发生模块和顶层模块。程序无BUG,可以直接使用