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FIR-filter-VHDL-code
- 基于FPGA的17阶FIR滤波器VHDL代码。文件附带了FIR数字滤波器理论的介绍。-FPGA-based 17-order FIR filter VHDL code. File with the FIR digital filter theory introduction.
daima
- fir滤波器的代码实现，最好使用quartus ii开发工具-Fir filter code realization, had better use quartus ii development tools
fir
- 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
fir_Verilog
- 用Verilog编写的fir滤波器程序！-Verilog prepared using the procedure fir filter!
bandpass-filter
- 这是一篇关于带通滤波器的毕业设计论文，涵盖IIR与FIR滤波器的设计！-This is an article on the band-pass filter design graduate thesis, covering IIR and FIR filter design!
dds
- 这是一个用vhdl语言实现dds的例子，已在quartusII里调通并可以下载到实验箱上，功能正确-This is a use of VHDL language dds example, has been in tune quartusII pass and can be downloaded to the experimental box, the function correctly
fir_gen
- 数字信号处理的fpga实现，用VHDL语言编程实现FIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve FIR filter
sdram_vhd
- FPGA设计的SDRAM控制器，有仿真代码，已通过验证-FPGA Design of SDRAM controller, there is simulation code has been validated
coeff_rom_1_6
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
coeff_rom_2_5
- FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
ruan
- 扩频发射机，信道编码采用(2, 1, 7)卷积 码, 扩频模块采用扩频长度255 的kasami码, 极性变换模块为3bit 量化模式, 内插模块为每两比特间插入7bit 和输出滤波为16 阶的FIR 滤波器。-direct sequence spread spectrum transmitter
coe
- 自动计算fir滤波器系数的工具，不妨一试-Automatic calculation of filter coefficients fir tools, try
fir_16
- vhdl代码 实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
fir_rtl
- Simple fir digital filter
case4
- DA算法中的使用的查找表模块，本程序先设计查找表，然后设计4*4DA算法模块，之后进行位扩展和字扩展得到32阶滤波器程序.附带4各表，和FIR滤波器序数-DA algorithm used in the lookup table module, the design of the program first look-up table, and then design 4* 4DA algorithm module, after the word-bit expansion and extens
IIR
- 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
filter_final
- compiled vhdl code for fir filter
VHDL_FPGA_FILTER
- 用VHDL语言设计基于FPGA器件的高采样率FIR滤波器,基于VHDL与CPLD器件的FIR数字滤波器的设计-Design using VHDL language FPGA devices based on high sampling rate FIR filter, based on VHDL and CPLD devices, the design of FIR digital filter
beta
- Fir verilog code implemented to find out the output of fir filter