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decoder
- 3_8decoder verilog module
LIP1759CORE_audio_dsp32_decoder
- Audio DSP32 Decoder Verilog Module
dct01
- Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
nova_latest.tar
- VERILOG source code of a H.264 baseline decoder.
decoder
- this the code for decoder in verilog-this is the code for decoder in verilog
Cabad
- MPEG-4/AVC - H.264 CABAC decoder written in VHDL and synthesis on a Virtex 5
Viterbi_Verilog
- viterbi译码的verilog实现,提供相应的原程序代码和testbench -viterbi decoder verilog implementation
ps_decoder3_12_80_mod
- PS-LDPC码译码器的Verilog程序-PS-LDPC code decoder of the Verilog program
RS
- RS译码器的设计源程序--verilog HDL实现-Design of the RS decoder source code-- Verilog HDL
Jpeg_decoder
- It is jpeg_decoder program. Source code are C and Verilog HDL.File .c reads data from jpeg and convert it to binary bit stream.Decoder is by verilog file
verilog
- Verilog初学者例程:1位全加器行为级设计、1位全加器门级设计、4位超前进位加法器、8位bcd十进制加法器、8位逐次进位加法器、16位超前进位加法器、16位级联加法器、多路四选一门级设计、七段译码器门级设计-Verilog routines for beginners: a behavioral-level design full adder, a full adder gate-level design, 4-ahead adder, decimal 8-bit bcd adder, 8-
i2c_1.tar
- i2c driver for video decoder ad9980 in virtex
decoder
- coder for different modules in verilog
decoder-and-encoder
- codes for different modules in verilog
Decoder-3x8
- Decoder 3x8 Verilog code... This is for Xilinx Spartan 3E board
decoder
- decoder code in verilog/vhdl language
decoder
- 对于通信传输中常用的曼彻斯特编码给出了详细的Verilog程序，程序在Modelsim中调试通过。-For the transmission of commonly used Manchester coding are also given Verilog process, the process of debugging in Modelsim through.
decoder
- Verilog编写数字编码器，还有激励输入的代码-Verilog prepared encoder, as well as excitation input code
38-decoder
- 3-8译码器的Verilog硬件语言实现，开发环境是ModelSim-The 3-8 decoder Verilog hardware language development environment is ModelSim