搜索资源列表
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
sgs32
- Verlog HDL 写得一款32路方波发生器，例子是4路可以自己加，相位可调，频率可调，占空比可调。具体参见readme.doc.此处只提供了源码包含顶层模块sgs32.v 子模块dds.v和pll设置模块altp.v及波形驱动文件-Verlog HDL write a 32 square-wave generator, for example, is able to add 4-way, phase adjustable, adjustable frequency, adjustable d
DSP
- 从算法设计到硬线逻辑的实现：复杂数字逻辑系统的Verilog HDL设计技术和方法，结合DSP算法介绍verilog HdL 设计。-From algorithm design to achieve hard-wired logic: complex digital logic system Verilog HDL design techniques and methods, combined with DSP algorithm design verilog HdL introduced.
dds
- 直接频率合成器，采用verilog hdl-Direct frequency synthesizer using verilog hdl
div16
- 十六位的除法器，采用verilog hdl-16 of the divider using verilog hdl
S8_VGA
- VGA的verilog hdl 程序，完成显示长条状显示不同颜色-VGA s verilog hdl procedures, completion of a long strip show show different color
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
GFmultiply
- Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
1-in_clk
- Verilog HDL编写的4条指令CPU-Verilog HDL prepared four instructions CPU
led_display
- 基于Verilog HDL的流水灯程序设计-Verilog HDL-based design flow lights
fftshixian
- OFDM系统中FFT的Verilog HDL 语言实现。-OFDM system FFT of Verilog HDL language.
verilog_hdl
- 精通verilog_hdl语言编程实例程序代码，基于verilog硬件语言的程序设计实例，主要是数字电路方面-Verilog_hdl proficient in language programming examples of program code, based on the Verilog hardware design language of the procedure, the main aspects of digital circuit
color_space_converters
- Color space converter in Verilog HDL
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
Music_LiangZhu
- FPGA音乐试验，语言：verilog HDL-A FPGA expperientation which can play music Liangzhu，language：verilog HDL
can
- 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
veriloghdl_teaching_model
- Verilog HDL权威教程，建模实例及语法参考和其他论题- Authority Verilog HDL tutorials , modeling examples and reference grammar ，other topics.
CCD_DRIVER
- verilog HDL语言，线性CCD1501D驱动程序，基于FPGA，其他线性传感器可参照修改。-verilog HDL language, linear CCD1501D driver, based on the FPGA, the other linear sensor can be modified by reference.
sha256_512
- Verilog实现的SHA256/SHA512算法，已仿真和验证-Verilog implementation of SHA256/SHA512 algorithm, simulation and verification has been done.