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Tomasulo2
- 用verilog编写流水CPU。采用Tomasulo算法，进一步的减少了等式右边的各项暂停时间，并通过阅读文献，实现了一种基于此算法原理的机器PowerPC 620的CPU的雏形-Tomasulo Based Speculative Processor
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
SCMIPS
- 使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
sARM01_07_12_2
- verilog hdl实现的ARM处理器-ARM processor implement by verilog HDL
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
i2c
- 用verilog写的I2C源码，对于学习硬件语言和处理器及总线相关知识有很大帮助。-I2C source code, written with verilog language and learning hardware processor and bus-related knowledge.
cpu
- 用verilog语言写的简单cpu，在处理器功能和结构上，对于初学者有很大帮助。-Verilog language write simple cpu, processor function and structure of great help for beginners.
ASSIGNMENT3
- Implementation of risc processor program in verilog coding.-Implementation of risc processor program in verilog coding.
Pipeline-2.zip
- Pipeline processor verilog components ,Pipeline processor verilog components
Pipeline-3.zip
- Verilog codes for pipelined processor,Verilog codes for pipelined processor
s_mips
- FPGA verilog mips processor - pipeline reference
cpu
- 用system verilog写的一个arm处理器原代码。-Write an ARM processor system verilog source code.
LBC_Avalon2.0_SOPC
- 基于SOPC Builder, EP3C40系列FPGA的Avalon总线和MPC8349处理器本地总线LBC，采用Verilog编写的Avalon总线与LBC的转换接口。-Based on SOPC Builder, EP3C40 FPGA family Avalon bus and MPC8349 Processor Local Bus LBC, using Verilog prepared with LBC conversion Avalon bus interface.
seg7
- fpga上nios处理器avalon总线数码管驱动，包含任务逻辑，寄存器，和接口的verilog HDL描述-fpga nios processor avalon bus on digital tube driver, including the task logic, registers, and interfaces verilog HDL descr iption
grayscale
- 灰階(gray-scale)圖像處理(60*60 pixel)controller控制各個程式的地址以及開關，input_mem將資料讀進記憶體，grayscale將讀取資料像素的亮度以數值來表示，將24bit的 像素化成四個8bit的值輸出。接著進入sobel，在此將前面的四個值乘上1或-1個別的相加，得出新的四個值，輸入進shiftcase進行threshold的判斷，大於threshold則表現出白色(255)，小於threshold則表現出黑色(0)，最後將結果存入記憶體out_mem。
simple
- 一个简单的8位处理器完整设计过程及verilog代码,适合初 学ic设计的人用，并含有我个人写的指令执行过程，仅供参 考-A simple 8-bit processor and the complete design process verilog code, suitable for beginners ic design for human use, and contains my personal writing instruction execution, for ref
uC_CISC_16_Design
- Verilog Based CISC Processor.....Availble for Purchase...rahulshandilya@outlook.com
ME-Project-Reference
- This project used code verilog to load on Kit Xilinx Spartan 3A. Wireless Sensor Nodes Processor Architecture and Design.I prefered on the internet
MIPS
- MIPs Processor in Verilog
4weizhucijinweijiafaqi_verilog
- 四位逐次进位加法器的verilog实现。附tb.v文件。单片机开发，数字逻辑与处理器基础实验-Four successive carry adder verilog implementation. Tb.v attached file. SCM development, digital logic and processor basic experiment