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Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
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介绍了一种硬件控制的自动数据采集系统的设计方法，包括数字系统自顶向下
(1DP—DOwN)的设计思路，Vernog}Ⅱ)L对系统硬件的描述和状态机的设计-Introduced a hardware-controlled automated data acquisition system design, including digital systems from top to bottom (1DP-DOwN) design ideas, Vernog} Ⅱ) L of the system
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VERILOG 语言写的使用状态机实现奇数分频-VERILOG language is written by the state machine to implement an odd number of points frequency
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设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
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the two pdf describe the state maceine designing with VHDL or Verilog! The examples are very good with your work!
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实现米粒状态机
用verilog语言实现状态机的过程-Implement a state machine with a grain of rice verilog state machine language course
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verilog 应用状态机设计的序列检测器-verilog ，state machine
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状态机程序，具有简易功能的自动贩卖机verilog hdl-Program of the state machine, vending machine with a simple function verilog hdl
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用Verilog语言编写带有特定序列的检测功能-Verilog language with a specific sequence detection function
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AD0804的控制程序，有VHDL和verilog两个方式。还有AD0804的介绍，和状态机控制-AD0804 control program, there are two ways to VHDL and verilog. There AD0804 introduction, and the state machine control
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Finate State machine
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verilog状态机实现并串转换serial_to_para,本人已调试并仿真成功，绝对可用-verilog state machine and string conversion，i think it is very important to someone who is ready to learn verilog
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verilog状态机实现的序列检测器，本人仿真通过，绝对可用，欢迎大家下载学习。-verilog state machine sequence detector simulation by himself, absolutely free, welcome to download the study.
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基于Verilog的四位密码锁设计，采用有限状态机进行编写-The four locks Verilog-based design, finite state machine for the preparation
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用verilog状态机写的IIC通信模块，包括两个子模块和一个顶层模块，均为verilog源码-Written in verilog state machine IIC communication module, including two modules and a top-level module, they are all the verilog code.
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智能洗衣机控制器 基于verilog hdl状态机 具有多种功能切换-Intelligent washing machine controller verilog hdl-based state machine has multi-functional switch
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State machine implemented in verilog to find GCD of two 8 bit numbers.
Two files are included (module and its testbench)
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verilog实例分析第三部分，通过实例分析讲解有限状态机的设计过程。-The third case study verilog part, by an example to explain the finite state machine design process.
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32位除法器，基于状态机设计，使用Verilog实现-32-bit division based on state machine. Using Verilog
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用于检测序列10010的程序，Verilog的状态机练习-Used to test series 10010 program, Verilog state machine practice
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