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multiply_verilog
- 几个常用的乘法器的verilog实现,包括普通乘法器,时序乘法器,行波乘法器-Several commonly used multiplier verilog achieve, including ordinary multiplier, multiplier timing, traveling wave multiplier, etc.
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
wave_freq
- 在VHDL/verilog环境下产生可调频率的波形,如三角波,方波,矩形波,同时支持计数功能,供参考-Adjustable frequency waveform generator in VHDL/verilog environment, such as triangle wave, square wave, rectangular wave, while supporting the counting function, for reference
module-counter8
- 用verilog实现8为计数器频率范围20-80kHz,根据DDS原理来一个时钟计数器记一下,n=n+1,根据公式fout=(fc÷x)÷2,fout=80 fc=320,所以n≥2时,再取反,又由公式 fout=(k.fc)÷2^n,k=50hz,fout=80khz,fc=320,所以数据的位宽n≥7。 设计要求两路方波信号的相位差在0-360゜可调,可以根据延时来实现。具体的-8 is realized with verilog counter frequency range 20-8
pwm
- VERILOG 学习第一课,输出一定占空比方波-VERILOG learn the first lesson, a certain duty cycle square wave output
dds
- 在altera的FPGA上实现直接数字频率合成,即用verilog实现DDS,输出正弦波形,在modelsim软件中仿真通过,已包含所有代码和工程以及二进制流文件。-The realization of direct digital frequency synthesis in the Altera FPGA, which is implemented by Verilog DDS, the output sine wave, through the simulation in Modelsim
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序,发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
SIN_GNT
- LPM_ROM定制。简单的正弦波发生器。 Verilog HDL语言设计。 EP4CE15F17C18N实测可用。-LPM_ROM customization. Simple sine wave generator. Verilog HDL designs. EP4CE15F17C18N measurement available.
DDS2
- 基于Verilog语言的正弦波的产生,应用了基于直接数字频率合成器的方法。-Verilog language generated based on the sine wave, the frequency of application of the direct digital synthesizer based methods.
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
NCO_test
- FPGA的压控振荡器NCO完整Verilog工程代码,测试输出1KHZ sin波。signaltap抓取没问题。-VCO NCO complete FPGA Verilog code engineering, test output 1KHZ sin wave. signaltap crawl no problem.
wave_gen
- 波形发生器,可以产生正弦波,锯齿波,方波。Verilog语言编写-Waveform generator, can generate sine wave, sawtooth wave, square wave. Verilog language
SinGen
- 使用Verilog编写的正弦波生成工程,使用ROM核产生,利用mif文件-Written using Verilog sine wave generation projects using ROM nuclear generation, use mif file
sin_quartus9.0
- 用Verilog实现不同相位的正弦波波形输出,使用到ROM查表方式,对不同相位的地址进行合成后查表得到不同相位的正弦波。-Implementation of Sine wave output with different phase.
DDS_sin
- 这是一个用Verilog编写的以实现DDS功能的程序,包含了正弦、方波、锯齿波。-This is a Verilog written procedures to implement DDS functions, including sine, square wave, sawtooth.
Triangle
- 在ISE环境下,使用Verilog语言,编写三角波程序,运用ModelSim进行仿真。-In the ISE environment, use Verilog language, written in a triangular wave program, using ModelSim simulation.
sine
- FPGA实现正弦波信号的产生,verilog语言-FPGA realization generate sine wave signal, verilog language
PWM
- 用FPGA,NOIS II和verilog一起输出矩形波-Output the rectangular wave
squa
- Verilog语言ISE下实现方波产生和占空比调节-ISE Verilog language implementations under wave generator
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序(已验证)Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files